library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jpxz is
port(clk:in std_logic;
    pc:in std_logic;
    pp:out std_logic);
end;
architecture jiep of jpxz is
signal ppl:std_logic;
signal ph:std_logic;
signal pl:std_logic;
begin
fenp:process(clk)
begin
if clk'event and clk='1'
then ppl<=not ppl;
end if;
end process;
ph<=clk;
pl<=ppl;
pp<=(not pc and pl)or(pc and ph);
end;