Project Information                                            c:\work\top.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/28/2009 11:10:46

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

top       EPM3128ATC100-5  1        32       0      75      71          58 %

User Pins:                 1        32       0  



Project Information                                            c:\work\top.rpt

** PROJECT COMPILATION MESSAGES **

Warning: GLOBAL primitive on node 'CLK' feeds logic -- non-global signal usage may result


Project Information                                            c:\work\top.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLK' chosen for auto global Clock


Project Information                                            c:\work\top.rpt

** FILE HIERARCHY **



|jpxz:4|
|cai_lizi:27|
|cai_lizi:27|lpm_add_sub:102|
|cai_lizi:27|lpm_add_sub:102|addcore:adder|
|cai_lizi:27|lpm_add_sub:102|altshift:result_ext_latency_ffs|
|cai_lizi:27|lpm_add_sub:102|altshift:carry_ext_latency_ffs|
|cai_lizi:27|lpm_add_sub:102|altshift:oflow_ext_latency_ffs|
|cai_bmq:28|


Device-Specific Information:                                   c:\work\top.rpt
top

***** Logic for device 'top' compiled without errors.




Device: EPM3128ATC100-5

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffffffff
    MultiVolt I/O                              = OFF

              R R R R R   R R R             R R R                
              E E E E E   E E E             E E E                
              S S S S S   S S S V           S S S   q   q   q q  
              E E E E E   E E E C           E E E V o q o   o o  
              R R R R R   R R R C           R R R C u o u   u u  
              V V V V V G V V V I G G G C G V V V C t u t G t t  
              E E E E E N E E E N N N N L N E E E I 1 t 2 N 2 2  
              D D D D D D D D D T D D D K D D D D O 9 0 0 D 1 2  
            ----------------------------------------------------_ 
           / 100  98  96  94  92  90  88  86  84  82  80  78  76   |_ 
          /     99  97  95  93  91  89  87  85  83  81  79  77    | 
RESERVED |  1                                                    75 | qout31 
RESERVED |  2                                                    74 | GND 
   VCCIO |  3                                                    73 | #TDO 
    #TDI |  4                                                    72 | RESERVED 
RESERVED |  5                                                    71 | qout12 
RESERVED |  6                                                    70 | qout8 
RESERVED |  7                                                    69 | qout6 
RESERVED |  8                                                    68 | qout7 
RESERVED |  9                                                    67 | qout5 
RESERVED | 10                                                    66 | VCCIO 
     GND | 11                                                    65 | GND 
RESERVED | 12                                                    64 | qout4 
RESERVED | 13                  EPM3128ATC100-5                   63 | qout3 
RESERVED | 14                                                    62 | #TCK 
    #TMS | 15                                                    61 | RESERVED 
RESERVED | 16                                                    60 | RESERVED 
RESERVED | 17                                                    59 | GND 
   VCCIO | 18                                                    58 | qout18 
RESERVED | 19                                                    57 | RESERVED 
RESERVED | 20                                                    56 | qout17 
RESERVED | 21                                                    55 | RESERVED 
RESERVED | 22                                                    54 | qout16 
  qout11 | 23                                                    53 | GND 
  qout13 | 24                                                    52 | qout15 
   qout9 | 25                                                    51 | VCCIO 
         |      27  29  31  33  35  37  39  41  43  45  47  49  _| 
          \   26  28  30  32  34  36  38  40  42  44  46  48  50   | 
           \----------------------------------------------------- 
              G R q q q q q G V q q q G V R R R G R R q q q q R  
              N E o o o o o N C o o o N C E E E N E E o o o o E  
              D S u u u u u D C u u u D C S S S D S S u u u u S  
                E t t t t t   I t t t   I E E E   E E t t t t E  
                R 1 2 1 3 2   O 2 2 2   N R R R   R R 2 2 2 1 R  
                V     4 0 9     8 6 3   T V V V   V V 4 5 7 0 V  
                E                         E E E   E E         E  
                D                         D D D   D D         D  


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                   c:\work\top.rpt
top

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   0/10(  0%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   1/10( 10%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     3/16( 18%)   4/10( 40%)  16/16(100%)   9/36( 25%) 
D:    LC49 - LC64     8/16( 50%)   8/ 9( 88%)  14/16( 87%)  20/36( 55%) 
E:    LC65 - LC80    16/16(100%)   4/10( 40%)  16/16(100%)  17/36( 47%) 
F:    LC81 - LC96    16/16(100%)   5/ 9( 55%)  16/16(100%)  13/36( 36%) 
G:   LC97 - LC112    16/16(100%)   8/ 9( 88%)  16/16(100%)  16/36( 44%) 
H:  LC113 - LC128    16/16(100%)   6/ 9( 66%)  16/16(100%)  15/36( 41%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            36/76     ( 47%)
Total logic cells used:                         75/128    ( 58%)
Total shareable expanders used:                 71/128    ( 55%)
Total Turbo logic cells used:                   75/128    ( 58%)
Total shareable expanders not available (n/a):  23/128    ( 17%)
Average fan-in:                                  7.37
Total fan-in:                                   553

Total input pins required:                       1
Total output pins required:                     32
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     75
Total flipflops required:                       10
Total product terms required:                  315
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          51

Synthesized logic cells:                        33/ 128   ( 25%)



Device-Specific Information:                                   c:\work\top.rpt
top

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  87      -   -       INPUT  G            0      0   0    0    0    0    1  CLK


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                                   c:\work\top.rpt
top

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  80    121    H     OUTPUT      t        0      0   0    0    7    0    0  qout0
  28     62    D     OUTPUT      t        2      2   0    0    9    0    0  qout1
  29     61    D     OUTPUT      t        3      3   0    0    9    0    0  qout2
  63     97    G     OUTPUT      t        2      1   1    0   10    0    0  qout3
  64     99    G     OUTPUT      t        3      2   1    0   11    0    0  qout4
  67    102    G     OUTPUT      t        2      1   1    0   11    0    0  qout5
  69    105    G     OUTPUT      t        3      2   1    0   11    0    0  qout6
  68    104    G     OUTPUT      t        3      3   0    0   10    0    0  qout7
  70    107    G     OUTPUT      t        3      0   1    0    7    0    0  qout8
  25     33    C     OUTPUT      t        7      5   0    0    9    0    0  qout9
  49     78    E     OUTPUT      t        5      4   1    0    8    0    0  qout10
  23     37    C     OUTPUT      t        7      3   1    0    9    0    0  qout11
  71    109    G     OUTPUT      t        4      3   1    0    8    0    0  qout12
  24     35    C     OUTPUT      t        6      3   1    0    9    0    0  qout13
  30     59    D     OUTPUT      t        5      2   0    0    9    0    0  qout14
  52     81    F     OUTPUT      t        5      2   1    0    8    0    0  qout15
  54     85    F     OUTPUT      t        2      1   1    0   10    0    0  qout16
  56     88    F     OUTPUT      t        3      1   1    0   11    0    0  qout17
  58     91    F     OUTPUT      t        6      4   1    0   11    0    0  qout18
  81    123    H     OUTPUT      t        5      3   1    0   10    0    0  qout19
  79    120    H     OUTPUT      t        4      3   1    0   13    0    0  qout20
  77    117    H     OUTPUT      t        6      4   1    0   11    0    0  qout21
  76    115    H     OUTPUT      t        6      5   1    0   12    0    0  qout22
  37     49    D     OUTPUT      t        6      5   0    0    8    0    0  qout23
  46     73    E     OUTPUT      t        5      3   1    0    9    0    0  qout24
  47     75    E     OUTPUT      t        5      3   1    0   10    0    0  qout25
  36     51    D     OUTPUT      t        0      0   0    0    4    0    0  qout26