library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity szxgq16 is
port(clk:in std_logic;
qa,qb:in std_logic_vector(0 to 15);
qc:out std_logic_vector(0 to 4));
end szxgq16;
architecture szxgq16_arc of szxgq16 is
component xgq4
port(clk:in std_logic;
a,b:in std_logic_vector(0 to 3);
c:out std_logic_vector(0 to 3);
end component;
signal c1,c2,c3,c4:std_logic_vector(0 to 2);
signal cc:std_logic_vector(0 to 3);
signal ccc:std_logic_vector(0 to 3);
begin
u1:xgq4 port map(clk,qa(0 to 3),qb(0 to 3),c1);
u1:xgq4 port map(clk,qa(4 to 7),qb(4 to 7),c2);
u1:xgq4 port map(clk,qa(8 to 11),qb(8 to 11),c3);
u1:xgq4 port map(clk,qa(12 to 15),qb(12 to 15),c4);
process(clk)
begin
if(clk'event and clk='1')then
cc<=c1+c2;
ccc<=c3+c4;
end if;
if(clk'event and clk='1')then
qc<=cc+ccc
end if;
end process;
end szxgq16_arc;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all
entity xgq4 is
port(clk:in std_logic;
a,b:in std_logic_vector(0 to 3);
c:out std_logic_vector(0 to 2));
end xgq4;
architecture xgq4_arc of xgq4 is
begin
process(clk)
variable cc:std_logic_vector(0 to 3);
variable ccc:std_logic_vector(0 to 2);
begin
cc:="0000";
ccc:="000";
if(clk'event and clk='1')then
for i in 0 to 3 loop
cc(i):=a(i) xor b(i);
end loop;
end if;
if(clk'event and clk='1')then
for i in 0 to 3 loop
ccc:=ccc+cc(i);
end loop;
end if;
c<=ccc;
end process;
end xgq4_arc;