?? keyin.rpt
字號:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\work\max+plus_work\stopwatch\keyin.rpt
keyin
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 01 DFFE + 1 2 1 0 :5
- 3 - A 01 DFFE + 1 2 1 0 :7
- 5 - A 01 DFFE + 1 0 0 2 reset_temp1 (:9)
- 4 - A 01 DFFE + 0 1 0 1 reset_temp2 (:10)
- 2 - A 01 DFFE + 1 0 0 2 on_off_temp1 (:11)
- 6 - A 01 DFFE + 0 1 0 1 on_off_temp2 (:12)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\work\max+plus_work\stopwatch\keyin.rpt
keyin
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\max+plus_work\stopwatch\keyin.rpt
keyin
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk1
INPUT 2 clk
Device-Specific Information: d:\work\max+plus_work\stopwatch\keyin.rpt
keyin
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
on_off : INPUT;
reset : INPUT;
-- Node name is ':11' = 'on_off_temp1'
-- Equation name is 'on_off_temp1', location is LC2_A1, type is buried.
on_off_temp1 = DFFE( on_off, GLOBAL(!clk1), VCC, VCC, VCC);
-- Node name is ':12' = 'on_off_temp2'
-- Equation name is 'on_off_temp2', location is LC6_A1, type is buried.
on_off_temp2 = DFFE( on_off_temp1, GLOBAL(!clk1), VCC, VCC, VCC);
-- Node name is 'on_off0'
-- Equation name is 'on_off0', type is output
on_off0 = _LC3_A1;
-- Node name is ':9' = 'reset_temp1'
-- Equation name is 'reset_temp1', location is LC5_A1, type is buried.
reset_temp1 = DFFE( reset, GLOBAL(!clk1), VCC, VCC, VCC);
-- Node name is ':10' = 'reset_temp2'
-- Equation name is 'reset_temp2', location is LC4_A1, type is buried.
reset_temp2 = DFFE( reset_temp1, GLOBAL(!clk1), VCC, VCC, VCC);
-- Node name is 'reset0'
-- Equation name is 'reset0', type is output
reset0 = _LC1_A1;
-- Node name is ':5'
-- Equation name is '_LC1_A1', type is buried
_EQ001 = clk1 & reset_temp1 & !reset_temp2;
-- Node name is ':7'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clk1 & on_off_temp1 & !on_off_temp2;
Project Information d:\work\max+plus_work\stopwatch\keyin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,400K
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