library ieee;
use ieee.std_logic_1164.all;
entity keyin is
	port(reset	:in std_logic;
			on_off	:in std_logic;
			clk		:in std_logic;
			clk1	:in std_logic;
			reset0	:out std_logic;
			on_off0	:out std_logic
			);
end keyin;

architecture rtl of keyin is
	signal reset_temp1	:std_logic;
	signal reset_temp2	:std_logic;
	signal reset_temp3	:std_logic;
	signal on_off_temp1	:std_logic;
	signal on_off_temp2	:std_logic;
	signal on_off_temp3	:std_logic;
begin
	process(clk1)
	begin
		if(clk1'event and clk1='0')then
			reset_temp1<=reset;
			reset_temp2<=reset_temp1;
			on_off_temp1<=on_off;
			on_off_temp2<=on_off_temp1;
		end if;
	end process;
	
	reset_temp3<=NOT reset_temp2;
	on_off_temp3<=NOT on_off_temp2;

	process(clk)
	begin
		if(clk'event and clk='1')then
			reset0<=clk1 and reset_temp1 and reset_temp3;
			on_off0<=clk1 and on_off_temp1 and on_off_temp3;
		end if;
	end process;
end rtl;