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--
-- Title       : Test Bench for parity_verifier
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
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--
-- File        : $DSN\src\TestBench\parity_verifier_TB.vhd
-- Generated   : 4/12/2005, 4:03 PM
-- From        : $DSN\src\parity_verifier.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for parity_verifier_tb
--
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library ieee;
use work.uart_package.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity parity_verifier_tb is
	-- Generic declarations of the tested unit
		generic(
		DATA_LENGTH : INTEGER := 8;
		PARITY_RULE : PARITY := EVEN );
end parity_verifier_tb;

architecture TB_ARCHITECTURE of parity_verifier_tb is
	-- Component declaration of the tested unit
	component parity_verifier
		generic(
		DATA_LENGTH : INTEGER := 8;
		PARITY_RULE : PARITY := none );
	port(
		source : in std_logic_vector((DATA_LENGTH-1) downto 0);
		parity : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal source : std_logic_vector((DATA_LENGTH-1) downto 0);
	-- Observed signals - signals mapped to the output ports of tested entity
	signal parity : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : parity_verifier
		generic map (
			DATA_LENGTH => DATA_LENGTH,
			PARITY_RULE => PARITY_RULE
		)

		port map (
			source => source,
			parity => parity
		);

	-- Add your stimulus here ...	   

	-- 測試主流程
	main: process
	begin	  
		source <= "10101010";
		wait for 200 ns;
		source <= "10101000";				
		wait;
		
	end process;
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_parity_verifier of parity_verifier_tb is
	for TB_ARCHITECTURE
		for UUT : parity_verifier
			use entity work.parity_verifier(parity_verifier);
		end for;
	end for;
end TESTBENCH_FOR_parity_verifier;