?? counter.vhd
字號:
-- 庫聲明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- 實體聲明
entity counter is
generic (
MAX_COUNT : integer := 10 );
port (
clk : in std_logic;
reset_n : in std_logic;
ce : in std_logic;
overflow : out std_logic );
end counter;
--}} End of automatically maintained section
-- 結構體
architecture counter of counter is
signal count : integer;
begin
-- enter your statements here --
-- 主過程
main: process( clk, reset_n )
begin
-- 判斷復位信號
if reset_n = '0' then
count <= 0;
overflow <= '0';
-- 時鐘信號的上升沿動作
elsif rising_edge(clk) and ce = '1' then
-- 在計數上閾時候輸出提示信號overflow
if count = MAX_COUNT-1 then
count <= 0;
overflow <= '1';
-- 恢復提示信號overflow為低
elsif count = 0 then
count <= count+1;
overflow <= '0';
else
count <= count+1;
end if;
end if;
end process;
end counter;
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