Release 6.1i - xst G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.21 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s --> Reading design: vga_enh_top.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : vga_enh_top.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : vga_enh_topOutput Format                      : NGCTarget Device                      : xc2s300e-6-pq208---- Source OptionsTop Module Name                    : vga_enh_topAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : vga_enh_top.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO=========================================================================WARNING:Xst:1885 - LSO file is empty, default list of libraries is used=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "vga_wb_slave.v"Compiling include file "vga_defines.v"Module <vga_wb_slave> compiledCompiling source file "vga_fifo.v"Module <vga_fifo> compiledCompiling source file "vga_wb_master.v"Module <vga_wb_master> compiledCompiling source file "generic_spram.v"Compiling include file "timescale.v"WARNING:HDLCompilers:38 - generic_spram.v line 80 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_csm_pb.v"Module <generic_spram> compiledModule <vga_csm_pb> compiledCompiling source file "vga_clkgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_clkgen> compiledCompiling source file "vga_vtim.v"Compiling source file "vga_tgen.v"Module <vga_vtim> compiledModule <vga_tgen> compiledCompiling source file "vga_colproc.v"Compiling source file "vga_pgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_colproc> compiledModule <vga_pgen> compiledCompiling source file "generic_dpram.v"WARNING:HDLCompilers:38 - generic_dpram.v line 107 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_fifo_dc.v"Module <generic_dpram> compiledModule <vga_fifo_dc> compiledCompiling source file "vga_enh_top.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_enh_top> compiledNo errors in compilationAnalysis of file <vga_enh_top.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================WARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeAnalyzing top module <vga_enh_top>.WARNING:Xst:916 - vga_enh_top.v line 420: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 425: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 426: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 430: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 431: Delay is ignored for synthesis.ERROR:Xst:899 - vga_enh_top.v line 425: The logic for <sluint> does not match a known FF or Latch template.ERROR:Xst:899 - vga_enh_top.v line 426: The logic for <luint> does not match a known FF or Latch template.  Found 2 error(s). Aborting synthesis.--> Total memory usage is 48688 kilobytes