library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


--高速AD采集
entity hsad is
	port(
			clk:in std_logic;--系統(tǒng)時鐘
			DACclk:out std_logic;--DAC時鐘
			ADCclk:out std_logic;--ADC時鐘
			adin:in std_logic_vector(7 downto 0);--ADC數(shù)據(jù)
			daout:in std_logic_vector(7 downto 0)--DAC數(shù)據(jù)
		);
end entity hsad;	

architecture adc of hsad is

component pll50
	port(
		inclk0:in std_logic := '0';
		c0:out std_logic);
	end component;

signal dat:std_logic_vector(7 downto 0);
signal pllclk:std_logic;
	
	
begin
	--signal ad_dat:std_logic(7 downto 0);
	DACclk<=pllclk;
	ADCclk<=pllclk;
	process(clk)
	begin
		if clk'event and clk='1'  then
				
			dat <= adin;
			--daout <= dat;		
		end if;
	end process;
	pll50 port map(inclk0 => clk,c0 => pllclk);
end adc ;