module led1(mclk,led,da,clk_out);
input mclk;
output [3:0] led;
output clk_out;
reg [3:0] led;
reg [7:0] data;
input [7:0] da;
reg [2:0] count;
reg [2:0] state;
wire clk;
wire clk_out;
reg [24:0]clk_c;

always@(posedge mclk)
begin
		clk_c=clk_c+1'b1;
end
assign clk_out=clk_c[24]; ——通過編輯，可以改變AD采樣的時鐘頻率

always @ (negedge clk_out)
begin
		count=count+1'b1; 
end
assign clk=count[2];  ——控制LED顯示的頻率    

always @ (negedge clk)
if(state==0)
   begin
   data=da[7:0];
   led=data[7:4];
   state=state+1'b1;
   end
else if(state==5) 
   begin
   led=data[3:0];
   state=state+1'b1;
   end
else
state=state+1'b1;

endmodule