--
-- This file implements Register inference on signals in clocked processes.
-- In this example a flip-flop will be infered on the signal Q.
--
entity TEST is 
	port( D, CLK : in bit;
	      Q : out bit);
end TEST;
architecture T154 of TEST is
begin
	process(CLK)
	begin
		if (CLK'event and CLK='1') then
			Q <= D;
		end if;
	end process;
end T154;