H1L88 = H1_Pre_RD & (H1_Pre_WR # !H1_mWR) # !H1_Pre_RD & !H1_mRD & (H1_Pre_WR # !H1_mWR);


--W1_CMD_ACK is Sdram_Control_4Port:u6|control_interface:control1|CMD_ACK
W1_CMD_ACK = DFFEAS(W1L51, N2__clk0,  ,  ,  ,  ,  ,  ,  );


--H1L89 is Sdram_Control_4Port:u6|ST[0]~2690
H1L89 = H1L24 & (H1L88 # H1L23 & !W1_CMD_ACK) # !H1L24 & (H1L23 & !W1_CMD_ACK);


--H1L96 is Sdram_Control_4Port:u6|ST[2]~2691
H1L96 = H1L93 & H1L128 & !H1L23 & !H1L89;


--H1L90 is Sdram_Control_4Port:u6|ST[0]~2692
H1L90 = H1L24 # H1L124 & (!H1L22 # !H1_ST[0]);


--H1L91 is Sdram_Control_4Port:u6|ST[0]~2693
H1L91 = H1L89 & H1_ST[0] # !H1L89 & (H1L90 & !H1L23);


--H1L130 is Sdram_Control_4Port:u6|add~2855
H1L130 = H1_ST[3] & !H1L129 # !H1_ST[3] & (H1L129 # GND);

--H1L131 is Sdram_Control_4Port:u6|add~2856
H1L131 = CARRY(!H1L129 # !H1_ST[3]);


--H1L132 is Sdram_Control_4Port:u6|add~2857
H1L132 = H1_ST[4] & (H1L131 $ GND) # !H1_ST[4] & !H1L131 & VCC;

--H1L133 is Sdram_Control_4Port:u6|add~2858
H1L133 = CARRY(H1_ST[4] & !H1L131);


--H1L134 is Sdram_Control_4Port:u6|add~2859
H1L134 = H1_ST[5] & !H1L133 # !H1_ST[5] & (H1L133 # GND);

--H1L135 is Sdram_Control_4Port:u6|add~2860
H1L135 = CARRY(!H1L133 # !H1_ST[5]);


--H1L136 is Sdram_Control_4Port:u6|add~2861
H1L136 = H1_ST[6] & (H1L135 $ GND) # !H1_ST[6] & !H1L135 & VCC;

--H1L137 is Sdram_Control_4Port:u6|add~2862
H1L137 = CARRY(H1_ST[6] & !H1L135);


--H1L138 is Sdram_Control_4Port:u6|add~2863
H1L138 = H1_ST[7] & !H1L137 # !H1_ST[7] & (H1L137 # GND);

--H1L139 is Sdram_Control_4Port:u6|add~2864
H1L139 = CARRY(!H1L137 # !H1_ST[7]);


--H1L140 is Sdram_Control_4Port:u6|add~2865
H1L140 = H1_ST[8] & (H1L139 $ GND) # !H1_ST[8] & !H1L139 & VCC;

--H1L141 is Sdram_Control_4Port:u6|add~2866
H1L141 = CARRY(H1_ST[8] & !H1L139);


--H1L142 is Sdram_Control_4Port:u6|add~2867
H1L142 = H1_ST[9] $ H1L141;


--H1L110 is Sdram_Control_4Port:u6|ST[9]~2694
H1L110 = H1L142 & H1L93 & !H1L23 & !H1L89;


--H1L106 is Sdram_Control_4Port:u6|ST[7]~2695
H1L106 = H1L93 & H1L138 & !H1L23 & !H1L89;


--H1L104 is Sdram_Control_4Port:u6|ST[6]~2696
H1L104 = H1L93 & H1L136 & !H1L23 & !H1L89;


--H1L102 is Sdram_Control_4Port:u6|ST[5]~2697
H1L102 = H1L93 & H1L134 & !H1L23 & !H1L89;


--H1L100 is Sdram_Control_4Port:u6|ST[4]~2698
H1L100 = H1L93 & H1L132 & !H1L23 & !H1L89;


--H1L98 is Sdram_Control_4Port:u6|ST[3]~2699
H1L98 = H1L93 & H1L130 & !H1L23 & !H1L89;


--H1L108 is Sdram_Control_4Port:u6|ST[8]~2700
H1L108 = H1L93 & H1L140 & !H1L23 & !H1L89;


--H1L94 is Sdram_Control_4Port:u6|ST[1]~2701
H1L94 = !H1L89 & (H1L23 # H1L93 & H1L126);


--W1_SADDR[9] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[9]
W1_SADDR[9] = DFFEAS(H1_mADDR[9], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L34 is Sdram_Control_4Port:u6|command:command1|SA~490
V1L34 = V1_do_load_mode # W1_SADDR[9] & (V1_do_writea # V1_do_reada);


--W1_SADDR[10] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[10]
W1_SADDR[10] = DFFEAS(H1_mADDR[10], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L35 is Sdram_Control_4Port:u6|command:command1|SA~491
V1L35 = V1_do_load_mode # W1_SADDR[10] & (V1_do_writea # V1_do_reada);


--W1_SADDR[11] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[11]
W1_SADDR[11] = DFFEAS(H1_mADDR[11], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L36 is Sdram_Control_4Port:u6|command:command1|SA~492
V1L36 = W1_SADDR[11] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--W1_SADDR[12] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[12]
W1_SADDR[12] = DFFEAS(H1_mADDR[12], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L37 is Sdram_Control_4Port:u6|command:command1|SA~493
V1L37 = V1_do_load_mode # W1_SADDR[12] & (V1_do_writea # V1_do_reada);


--W1_SADDR[13] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[13]
W1_SADDR[13] = DFFEAS(H1_mADDR[13], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L38 is Sdram_Control_4Port:u6|command:command1|SA~494
V1L38 = V1_do_load_mode # W1_SADDR[13] & (V1_do_writea # V1_do_reada);


--W1_SADDR[14] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[14]
W1_SADDR[14] = DFFEAS(H1_mADDR[14], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L39 is Sdram_Control_4Port:u6|command:command1|SA~495
V1L39 = W1_SADDR[14] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--W1_SADDR[15] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[15]
W1_SADDR[15] = DFFEAS(H1_mADDR[15], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L40 is Sdram_Control_4Port:u6|command:command1|SA~496
V1L40 = W1_SADDR[15] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--W1_SADDR[16] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[16]
W1_SADDR[16] = DFFEAS(H1_mADDR[16], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L41 is Sdram_Control_4Port:u6|command:command1|SA~497
V1L41 = W1_SADDR[16] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--W1_SADDR[17] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[17]
W1_SADDR[17] = DFFEAS(H1_mADDR[17], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L42 is Sdram_Control_4Port:u6|command:command1|SA~498
V1L42 = W1_SADDR[17] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--V1L57 is Sdram_Control_4Port:u6|command:command1|always4~0
V1L57 = V1_do_writea # V1_do_reada;


--W1_SADDR[18] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[18]
W1_SADDR[18] = DFFEAS(H1_mADDR[18], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1_do_precharge is Sdram_Control_4Port:u6|command:command1|do_precharge
V1_do_precharge = DFFEAS(V1L53, N2__clk0,  ,  ,  ,  ,  , W1_INIT_REQ,  );


--V1_do_rw is Sdram_Control_4Port:u6|command:command1|do_rw
V1_do_rw = DFFEAS(V1L84, N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L43 is Sdram_Control_4Port:u6|command:command1|SA~499
V1L43 = V1L57 & W1_SADDR[18] & !V1_do_precharge & !V1_do_rw;


--W1_SADDR[19] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[19]
W1_SADDR[19] = DFFEAS(H1_mADDR[19], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L44 is Sdram_Control_4Port:u6|command:command1|SA~500
V1L44 = W1_SADDR[19] & !V1_do_load_mode & (V1_do_writea # V1_do_reada);


--H1L25 is Sdram_Control_4Port:u6|Equal~1121
H1L25 = H1_mRD & !H1_Pre_RD;


--H1L59 is Sdram_Control_4Port:u6|Read~463
H1L59 = H1L20 & H1L25 & !H1_ST[0] & !H1_ST[1];


--H1L121 is Sdram_Control_4Port:u6|Write~320
H1L121 = H1_Write & !H1L59 & (H1_ST[0] # !H1L22);


--H1L122 is Sdram_Control_4Port:u6|Write~321
H1L122 = H1L24 & H1_mWR & !H1_Pre_WR;


--H1L123 is Sdram_Control_4Port:u6|Write~322
H1L123 = H1L121 # H1L122 & !H1_Write & !H1L25;


--H1L26 is Sdram_Control_4Port:u6|Equal~1122
H1L26 = !H1L17 # !H1_ST[2] # !H1_ST[0];


--H1L60 is Sdram_Control_4Port:u6|Read~464
H1L60 = H1_Read & (H1L26 $ (!H1L59 & H1L122)) # !H1_Read & H1L59;


--V1_do_refresh is Sdram_Control_4Port:u6|command:command1|do_refresh
V1_do_refresh = DFFEAS(V1L55, N2__clk0,  ,  ,  ,  ,  , W1_INIT_REQ,  );


--V1L109 is Sdram_Control_4Port:u6|command:command1|rw_flag~24
V1L109 = !V1_do_load_mode & !V1_do_precharge;


--V1_rw_flag is Sdram_Control_4Port:u6|command:command1|rw_flag
V1_rw_flag = DFFEAS(V1L110, N2__clk0,  ,  ,  ,  ,  , W1_INIT_REQ,  );


--V1L46 is Sdram_Control_4Port:u6|command:command1|WE_N~73
V1L46 = V1_do_rw & !V1_do_writea & !V1_do_reada;


--V1L47 is Sdram_Control_4Port:u6|command:command1|WE_N~74
V1L47 = V1_do_refresh # V1L109 & (V1_rw_flag # !V1L46);


--V1L7 is Sdram_Control_4Port:u6|command:command1|CAS_N~114
V1L7 = !V1_do_refresh & (V1_do_precharge # !V1_do_load_mode & !V1L46);


--V1_oe4 is Sdram_Control_4Port:u6|command:command1|oe4
V1_oe4 = DFFEAS(V1L93, N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L15 is Sdram_Control_4Port:u6|command:command1|RAS_N~164
V1L15 = V1_do_precharge & (V1_rw_flag # V1_oe4);


--V1L16 is Sdram_Control_4Port:u6|command:command1|RAS_N~165
V1L16 = !V1_do_refresh & (V1L15 # V1L109 & !V1L57);


--W1_SADDR[22] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[22]
W1_SADDR[22] = DFFEAS(H1_mADDR[22], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1_do_initial is Sdram_Control_4Port:u6|command:command1|do_initial
V1_do_initial = DFFEAS(W1_INIT_REQ, N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L12 is Sdram_Control_4Port:u6|command:command1|CS_N~22
V1L12 = V1L109 & W1_SADDR[22] & !V1_do_refresh & !V1_do_initial;


--W1_SADDR[20] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[20]
W1_SADDR[20] = DFFEAS(H1_mADDR[20], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L4 is Sdram_Control_4Port:u6|command:command1|BA~32
V1L4 = W1_SADDR[20] & !V1_do_load_mode & !V1_do_precharge;


--W1_SADDR[21] is Sdram_Control_4Port:u6|control_interface:control1|SADDR[21]
W1_SADDR[21] = DFFEAS(H1_mADDR[21], N2__clk0,  ,  ,  ,  ,  ,  ,  );


--V1L5 is Sdram_Control_4Port:u6|command:command1|BA~33
V1L5 = W1_SADDR[21] & !V1_do_load_mode & !V1_do_precharge;


--PB2_END is I2C_AV_Config:u9|I2C_Controller:u0|END
PB2_END = DFFEAS(PB2L14, L1_mI2C_CTRL_CLK, KEY[0],  ,  ,  ,  ,  ,  );


--L1_mSetup_ST.0010 is I2C_AV_Config:u9|mSetup_ST.0010
L1_mSetup_ST.0010 = DFFEAS(L1L92, L1_mI2C_CTRL_CLK, KEY[0],  , L1L26,  ,  ,  ,  );


--L1_mSetup_ST.0001 is I2C_AV_Config:u9|mSetup_ST.0001
L1_mSetup_ST.0001 = DFFEAS(L1L28, L1_mI2C_CTRL_CLK, KEY[0],  , L1L26,  ,  ,  ,  );


--L1L27 is I2C_AV_Config:u9|Select~135
L1L27 = L1_mI2C_GO & (PB2_END # !L1_mSetup_ST.0001) # !L1_mI2C_GO & (!L1_mSetup_ST.0010 & !L1_mSetup_ST.0001);


--L1_LUT_INDEX[2] is I2C_AV_Config:u9|LUT_INDEX[2]
L1_LUT_INDEX[2] = DFFEAS(L1L9, L1_mI2C_CTRL_CLK, KEY[0],  , L1L18,  ,  ,  ,  );


--L1_LUT_INDEX[3] is I2C_AV_Config:u9|LUT_INDEX[3]
L1_LUT_INDEX[3] = DFFEAS(L1L12, L1_mI2C_CTRL_CLK, KEY[0],  , L1L18,  ,  ,  ,  );


--L1_LUT_INDEX[4] is I2C_AV_Config:u9|LUT_INDEX[4]
L1_LUT_INDEX[4] = DFFEAS(L1L15, L1_mI2C_CTRL_CLK, KEY[0],  , L1L18,  ,  ,  ,  );


--L1_LUT_INDEX[5] is I2C_AV_Config:u9|LUT_INDEX[5]
L1_LUT_INDEX[5] = DFFEAS(L1L19, L1_mI2C_CTRL_CLK, KEY[0],  , L1L18,  ,  ,  ,  );


--L1L26 is I2C_AV_Config:u9|LessThan~366
L1L26 = !L1_LUT_INDEX[2] & !L1_LUT_INDEX[3] # !L1_LUT_INDEX[5] # !L1_LUT_INDEX[4];


--L1_mI2C_CLK_DIV[1] is I2C_AV_Config:u9|mI2C_CLK_DIV[1]
L1_mI2C_CLK_DIV[1] = DFFEAS(L1L35, CLOCK_50, KEY[0],  ,  ,  ,  , L1L25,  );


--L1_mI2C_CLK_DIV[0] is I2C_AV_Config:u9|mI2C_CLK_DIV[0]
L1_mI2C_CLK_DIV[0] = DFFEAS(L1L32, CLOCK_50, KEY[0],  ,  ,  ,  , L1L25,  );


--L1L32 is I2C_AV_Config:u9|mI2C_CLK_DIV[0]~239
L1L32 = L1_mI2C_CLK_DIV[0] $ VCC;

--L1L33 is I2C_AV_Config:u9|mI2C_CLK_DIV[0]~240
L1L33 = CARRY(L1_mI2C_CLK_DIV[0]);


--L1L35 is I2C_AV_Config:u9|mI2C_CLK_DIV[1]~241
L1L35 = L1_mI2C_CLK_DIV[1] & !L1L33 # !L1_mI2C_CLK_DIV[1] & (L1L33 # GND);

--L1L36 is I2C_AV_Config:u9|mI2C_CLK_DIV[1]~242
L1L36 = CARRY(!L1L33 # !L1_mI2C_CLK_DIV[1]);


--L1L38 is I2C_AV_Config:u9|mI2C_CLK_DIV[2]~243
L1L38 = L1_mI2C_CLK_DIV[2] & (L1L36 $ GND) # !L1_mI2C_CLK_DIV[2] & !L1L36 & VCC;

--L1L39 is I2C_AV_Config:u9|mI2C_CLK_DIV[2]~244
L1L39 = CARRY(L1_mI2C_CLK_DIV[2] & !L1L36);


--L1L41 is I2C_AV_Config:u9|mI2C_CLK_DIV[3]~245
L1L41 = L1_mI2C_CLK_DIV[3] & !L1L39 # !L1_mI2C_CLK_DIV[3] & (L1L39 # GND);

--L1L42 is I2C_AV_Config:u9|mI2C_CLK_DIV[3]~246
L1L42 = CARRY(!L1L39 # !L1_mI2C_CLK_DIV[3]);


--L1L44 is I2C_AV_Config:u9|mI2C_CLK_DIV[4]~247
L1L44 = L1_mI2C_CLK_DIV[4] & (L1L42 $ GND) # !L1_mI2C_CLK_DIV[4] & !L1L42 & VCC;

--L1L45 is I2C_AV_Config:u9|mI2C_CLK_DIV[4]~248
L1L45 = CARRY(L1_mI2C_CLK_DIV[4] & !L1L42);


--L1L47 is I2C_AV_Config:u9|mI2C_CLK_DIV[5]~249
L1L47 = L1_mI2C_CLK_DIV[5] & !L1L45 # !L1_mI2C_CLK_DIV[5] & (L1L45 # GND);

--L1L48 is I2C_AV_Config:u9|mI2C_CLK_DIV[5]~250
L1L48 = CARRY(!L1L45 # !L1_mI2C_CLK_DIV[5]);


--L1L50 is I2C_AV_Config:u9|mI2C_CLK_DIV[6]~251
L1L50 = L1_mI2C_CLK_DIV[6] & (L1L48 $ GND) # !L1_mI2C_CLK_DIV[6] & !L1L48 & VCC;

--L1L51 is I2C_AV_Config:u9|mI2C_CLK_DIV[6]~252
L1L51 = CARRY(L1_mI2C_CLK_DIV[6] & !L1L48);


--L1L53 is I2C_AV_Config:u9|mI2C_CLK_DIV[7]~253
L1L53 = L1_mI2C_CLK_DIV[7] & !L1L51 # !L1_mI2C_C