//////////////////////////////////////////////////////////////////////////                                                              ////////  File name "test_bench.v"                                    ////////                                                              ////////  This file is part of the "PCI bridge" project               ////////  http://www.opencores.org/cores/pci/                         ////////                                                              ////////  Author(s):                                                  ////////      - mihad@opencores.org                                   ////////      - Miha Dolenc                                           ////////                                                              ////////  All additional information is avaliable in the README.pdf   ////////  file.                                                       ////////                                                              ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: test_bench.v,v $// Revision 1.5  2001/07/30 15:24:34  mihad// no message////// Common definitions for simulation purposes`define Tpci 75 // Tp/2 = 7.5ns => Tp = 15ns => Fpci = 66MHz`define Twb 25  // Tp/2 = 2.5ns =>   Tp = 5ns  => Fwb  = 200MHz//Running this test bench requires all include files in same directory`include "constants.v"`include "conf_space.v"`include "wb_slave.v"`include "wb_master32.v"`include "wbw_wbr_fifos.v"`include "wb_bus_mon.v"`include "bus_commands.v"`include "decoder.v"`include "delayed_sync.v"`include "delayed_write_reg.v"/*===================================================================================================This test bench is intended for HOST bridge implementation simulation. ( definition in constants.v )The reason is that configuration space operation, configuration and interrupt acknowledge cyclesrequest generation are also tested in this testbench. This features are only implemented in HOST bridge implementation. ===================================================================================================*/module TEST_BENCH () ;// clocksreg wb_clock ;reg pci_clock ;// resetreg reset ;/*==================================================================================================Simulated signals - signals on PCI side of the bridge are simulated in behavioral fashion==================================================================================================*/// read enable for wbw_fiforeg wbw_renable ;// write enable for wbr_fiforeg wbr_wenable ;// data input to wbr fiforeg [31:0] wbr_data_in ;// byte enable input to wbr fiforeg [3:0] wbr_be_in ;// control input to wbr fiforeg [3:0] wbr_control_in ;// pciw fifo empty indicatorreg pciw_empty ;// variable for feeding delayed trans. logic with status signalreg del_error_signal ;// variable for communicating to completing task that it should terminate with an errorreg error_terminate ;// pci delayed read completion pendingreg pci_drcomp_pending ;// lock simulation - signal locks out all but configuration accesses from WISHBONE busreg wbs_lock ;// pci side configuration space address, data and read enable signalsreg  [11:0] pci_conf_raddr ;reg         pci_conf_renable ;wire [31:0] pci_conf_data_probe ;// pci side completion simulation variablesreg del_comp_done, del_rty_exp;// variables for various error reporting mechanismsreg perr_set, serr_set, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err ;// outputs from configuration space for pci interfacewire [7:0] cache_line_size_probe ;wire [7:0] latency_tim_probe ;wire [2:0] int_pin_probe ;// pci address decoding values - just for checking since PCI side is only simulatedwire [19:0] pci_ba0, pci_ba1, pci_ba2, pci_ba3, pci_ba4, pci_ba5 ;wire [19:0] pci_am0, pci_am1, pci_am2, pci_am3, pci_am4, pci_am5 ;wire [19:0] pci_ta0, pci_ta1, pci_ta2, pci_ta3, pci_ta4, pci_ta5 ;wire [5:0]  pci_map ;wire [1:0]  pci_img_ctrl0, pci_img_ctrl1, pci_img_ctrl2, pci_img_ctrl3, pci_img_ctrl4, pci_img_ctrl5 ;// pci error reporting variables - simulatedreg [3:0]  pci_error_be ;reg [3:0]  pci_error_bc ;reg        pci_error_rty_exp ;reg        pci_error_sig ;reg [31:0] pci_error_addr ;reg [31:0] pci_error_data ;wire pci_error_rty_exp_set ;// error log enable signalwire pci_error_en ;// WISHBONE error reporting variablesreg [3:0] wb_error_be ;reg [3:0] wb_error_bc ;reg wb_error_rty_exp ;reg wb_error_es ;reg wb_error_sig ;reg [31:0] wb_error_addr ;reg [31:0] wb_error_data ;wire wb_error_rty_exp_set ;// interrupt status generationreg isr_int_prop ;reg isr_err_int  ;reg isr_par_err_int ;reg isr_sys_err_int ;/*============================================================================================Module interconnect signals - wires, buses, muxes for module interconnects============================================================================================*/// configuration hit wirewire conf_hit ;// delayed read bus command buswire [3:0] del_bc ;// data for delayed read requests and completionswire [31:0] del_addr ;wire [3:0]  del_be ;// delayed read flag wireswire    del_req,         del_comp,         read_in_burst,         pci_req ;// configuration space data input - from WISHBONE slave, since this is HOST implementation simulationwire [31:0] conf_data;// address from MUX, WISHBONE slave output and input data buses and SEL busreg     [31:0]  address ;// image access data and bus command/byte enable buseswire [31:0] image_data ;wire [3:0]  image_cbe ;// WISHBONE Write FIFO outputswire [31:0] wbw_data_probe ;wire [3:0]  wbw_cbe_probe ;wire [3:0]  wbw_control_probe ;// WISHBONE Read FIFO - WISHBONE slave interconnectwire [31:0] wbr_data ;wire [3:0]  wbr_be ;wire [3:0]  wbr_control ;// delayed read request bus command outputwire [3:0] del_bc_probe ;// configuration offset and byte enable interconnectwire [11:0] conf_offset_probe ;wire [3:0] conf_be_probe ;// configuration cycle address interconnectwire [23:0] config_addr ;// control bus interconnect between WBW_FIFO and WISHBONE slavewire [3:0] wbw_control ;// configuration space data outputwire [31:0] conf_data_probe ;// image hit signalswire [4:0] hit ;// WISHBONE bus interconnect between behav. master and WISHBONE slavewire    [31:0]  addr_o ;            // addresswire    [31:0]  sdat_o ;            // DAT_O from slavewire    [31:0]  sdat_i ;            // DAT_I to slavewire    [3:0]   sel ;               // SEL_I to slavewire            cyc ;               // CYC_I to slavewire            stb ;               // STB_I to slavewire            we  ;               // WE_I to slavewire            ack ;               // ACK_O from slavewire            rty ;               // RTY_O from slavewire            err ;               // ERR_O from slavewire            cab ;               // CAB_I to slave// map wireswire [5:1] wb_map ;// wb image control signalswire [2:0] wb_img_ctrl0, wb_img_ctrl1, wb_img_ctrl2, wb_img_ctrl3, wb_img_ctrl4, wb_img_ctrl5 ;wire [4:0] wb_mrl = { wb_img_ctrl5[0], wb_img_ctrl4[0], wb_img_ctrl3[0], wb_img_ctrl2[0], wb_img_ctrl1[0] } ;wire [4:0] wb_pref = { wb_img_ctrl5[1], wb_img_ctrl4[1], wb_img_ctrl3[1], wb_img_ctrl2[1], wb_img_ctrl1[1] } ;`ifdef FPGA    assign glbl.GSR = reset ;`endif// WISHBONE read FIFO flush wirewire wbs_wbr_flush, delayed_sync_wbr_flush ;wire wbr_flush = wbs_wbr_flush || delayed_sync_wbr_flush ;// memory for storing various data/*-----------------------------------------------------------------------------------------------------------------------------Memory is devided into four pieces - two for writes and two for reads - one of each for IO and one for MEMORY accesses.Test bench first copies data from Write memory, through WISHBONE slave and WBW_FIFO to simulated side of the bridge. This sidefills read memory. Then Test Bench reads data through WBR_FIFO and WISHBONE slave module and compares it to written data-----------------------------------------------------------------------------------------------------------------------------*/reg [31:0] wmem_data [0:1023] ; // data for memory mapped image writesreg [31:0] wio_data  [0:1023] ; // data for IO mapped image writesreg [7:0] rmem_data [0:4095] ;  // data for memory mapped image readsreg [7:0] rio_data  [0:4095] ;  // data for IO mapped image readsreg [31:0] conf_read_data ;     // data for configuration cycle read requestreg [31:0] iack_read_data ;     // data for interrupt acknowledge cycle read request// memory array for FIFO contents checking - FIFO contents is checked whenever something is read from itreg [39:0] wbw_contents[0:`WBW_DEPTH - 1] ;reg [`WBW_ADDR_LENGTH - 1:0] wbw_write_pointer ;reg [`WBW_ADDR_LENGTH - 1:0] wbw_read_pointer ;// WISHBONE slave interface instantiationWB_SLAVE wishbone_slave(