// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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// --------------------------------------------------------------------
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 12/08/98  :| Initial Creation
// --------------------------------------------------------------------
//
//	Module  config_mux
// This block implements the PCI target configuration registers, and
// the PCI data output MUX.  It controls when data gets written into the
// configuration registers, and what data gets presented onto the output
// data bus (pci_dat_out) during reads.
//
// Note:  The read values for the base address registers are set in this
//        block.  BA0 & BA1 always return the size of the memory block for the
//        backend app. when read. 
//

module config_mux (pci_dat_out, ba0_size, ba1_size, bkend_dat, 
                   pci_dat, pci_cbe_l, pci_addr, pci_rst_l, 
		   abort_sig, pci_clk, com, cbe_reg_l, 
		   idsel_reg, ba0_en, ba1_en, pci_irdy_l,
		   //JO ADD
		   ba0_rw_reg, ba1_rw_reg
		   //END JO ADD
		   );
 
  output [31:0] pci_dat_out; // the pci output data bus
  output [31:4] ba0_size; // The address space required for ba0
  output [31:4] ba1_size; // The address space required for ba1
  output [1:0] com; // The Mem - I/O enable bits of the command reg
  output ba1_en, ba0_en;
 
  input pci_irdy_l;
  input [3:0] cbe_reg_l;
  input idsel_reg;
  input [31:0] bkend_dat; // back end data in
  input [7:0] pci_addr;
  input [31:0] pci_dat; // pci data
  input [3:0] pci_cbe_l; // byte enables in

  input pci_rst_l; // async reset
  input abort_sig; // state machine is aborting set status
  input pci_clk; 
  //JO ADD
  input [31:0] ba0_rw_reg; 
  input [31:0] ba1_rw_reg;
  //END JO ADD

/******************************************************************/
// reg declarations
reg [7:0] int_line; // r/w interupt line register
reg [31:0] pci_dat_out; // output data bus
reg [31:0] cfg_dat_out; // output data bus
reg [1:0] com; // The command register
reg stat11; // The status register bit for signaled target abort
reg stat_com_en;
reg int_line_en;
reg ba1_en;
reg ba0_en;

wire cfg_en;
reg cfg_out;

/******************************************************************/


// The following parameters set the values for the read only 
// configuration registers.

/******************************************************************/
/************    Start Reg 00h Section              ***************/
/******************************************************************/
// reg 00h (DevID/VendorID)
parameter	DEVICE_ID     = 16'h0120; // User Defined
parameter	VENDOR_ID     = 16'h1022; // Set to AMD
/******************************************************************/
/************    End Reg 00h Section              *****************/
/******************************************************************/


/******************************************************************/
/************    Start Reg 04h Section              ***************/
/******************************************************************/
//reg 04h (status/command) 

// The only bits used in this section are status[11:9] 
// Command[1:0] The rest are all disabled to 0 at the Mux inputs

// `defines used for devsel
`define fast    2'b00
`define medium  2'b01
`define slow    2'b10
parameter DEV_SEL = `slow; // medium devsel timing

// The creation of the status and Command Registers
always @ (posedge pci_clk or negedge pci_rst_l)
  if (pci_rst_l == 1'b0) begin 
     com <= 2'b00; // disable I/O and MEM space accesses.
     stat11 <= 1'b0; // reset target abort status bit
  end
  else if (stat_com_en == 1'b1) begin 
      if (!pci_cbe_l[0])  // check to see if byte lane is enabled
        com <= pci_dat[1:0]; 
      else
        com <= com;
      if (!pci_cbe_l[3] && pci_dat[27]) // check to see if byte lane is enabled
        stat11 <= 0; // write a 1 clears this bit
      else
        stat11 <= stat11;    
  end 
  else if (abort_sig == 1'b1) begin 
     stat11 <= 1'b1; // set target abort status bit
     com <= com;
  end 
  else begin 
    stat11 <= stat11;
    com <= com;
  end
/******************************************************************/
/************    End Reg 04h Section              *****************/
/******************************************************************/



/******************************************************************/
/************    Start Reg 08h Section              ***************/
/******************************************************************/
// reg 08h (Class/revision)
parameter	CLASS_CODE    = 24'h058000;	// Memory Controller 
parameter	REVISION_ID   =  8'h01;		// Rev. 01
/******************************************************************/
/************    End Reg 08h Section              *****************/
/******************************************************************/



/******************************************************************/
/************    Start Reg 0Ch Section              ***************/
/******************************************************************/
// reg 0Ch (Misc Functions)
// No BIST, Type 00 header, Ignore Cachelinesize, No Latency Set,
parameter MISC_FUNCTIONS = 32'h00000000;

/******************************************************************/
/************    End Reg 0Ch Section              *****************/
/******************************************************************/




/******************************************************************/
/************  Start Base Address Defines Section   ***************/
/******************************************************************/

// Base address registers. 
// The Following `defines are used in the Base Address Parameters
// To set if the Back End Device is:
//   -User I/O or Memory
//   -Where it is locatated in the address map
//   -If the backend device is prefetchable
//   -How much address space it requires

`define MEM_ON         1'b0
`define IO_ON          1'b1

`define ANYWHERE_IN_32 2'b00
`define BELOW_1M       2'b01
`define ANYWHERE_IN_64 2'b10

`define PREFETCH_ON    1'b1
`define PREFETCH_OFF   1'b0

`define ADDR_2G     28'h8000_000
`define ADDR_1G     28'hC000_000
`define ADDR_512M   28'hE000_000
`define ADDR_256M   28'hF000_000
`define ADDR_128M   28'hF800_000
`define ADDR_64M    28'hFC00_000
`define ADDR_32M    28'hFE00_000
`define ADDR_16M    28'hFF00_000