module ac(din, clk, rst, acload, acinc, dout);
input [7:0] din;
input clk, rst, acload, acinc;
output [7:0] dout;
reg [7:0] dout;
always @(posedge clk)
	if(rst)
	dout=0;
	else if(acinc)
	dout=dout+1;
	else if(acload)
	dout=din;

endmodule