module ar(din,rst, arload, clk, dout);
input [5:0] din;
input arload, clk, rst;
output [5:0] dout;
reg [5:0] dout;
always@(posedge clk)
	if(rst)
	dout=0;
	else if(arload)
	dout=din;
	
endmodule