module dr(din, clk, rst, drload, dout);
input [7:0] din;
input clk, rst, drload;
output [7:0] dout;
reg [7:0]dout;
always @(posedge clk or posedge rst)
	if(rst)
	dout=0;
	else if(drload)
	dout=din;

endmodule