module alu(ac, dr, alusel, acc);
input [7:0] ac,dr;
input alusel;
output [7:0] acc;
reg [7:0] acc;
always@(ac or dr or alusel)
if(alusel)
	begin
   	acc[0]=ac[0]&&dr[0];
	acc[1]=ac[1]&&dr[1]; 
	acc[2]=ac[2]&&dr[2];
	acc[3]=ac[3]&&dr[3];
	acc[4]=ac[4]&&dr[4];
	acc[5]=ac[5]&&dr[5];
	acc[6]=ac[6]&&dr[6];
	acc[7]=ac[7]&&dr[7];
	end
else 
	acc=ac+dr;

endmodule