module pc(din, clk,rst, ld, inc, dout);
input [5:0]din;
input clk, ld, inc,rst;
output [5:0] dout;
reg [5:0] dout;
always @(posedge clk)
	if(rst)
	dout=0;
	else if(ld)
	dout=din;
	else if(inc)
	dout=dout+1;
	
endmodule