?? half_clk.pin
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-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 9: 3.3V
-- Bank 10: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. For transceiver I/O banks (Bank 13, 14, 15, 16 and 17),
-- connect each pin marked GND* either individually through a 10 kohm resistor
-- to GND or tie all pins together and connect through a single 10 kohm resistor
-- to GND.
-- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
CHIP "half_clk" ASSIGNED TO AN: EP2S15F484C3
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
TEMPDIODEp : A2 : : : : :
VCCIO4 : A3 : power : : 3.3V : 4 :
MSEL3 : A4 : : : : 4 :
GND* : A5 : : : : 4 :
GND* : A6 : : : : 4 :
GND* : A7 : : : : 4 :
GND* : A8 : : : : 4 :
GND : A9 : gnd : : : :
GND* : A10 : : : : 9 :
VCCIO4 : A11 : power : : 3.3V : 4 :
VCCIO3 : A12 : power : : 3.3V : 3 :
GND* : A13 : : : : 3 :
GND : A14 : gnd : : : :
GND* : A15 : : : : 3 :
GND* : A16 : : : : 3 :
GND* : A17 : : : : 3 :
GND* : A18 : : : : 3 :
GND* : A19 : : : : 3 :
VCCIO3 : A20 : power : : 3.3V : 3 :
nCE : A21 : : : : 3 :
GND : A22 : gnd : : : :
VCCIO6 : AA1 : power : : 3.3V : 6 :
GND : AA2 : gnd : : : :
nCEO : AA3 : : : : 7 :
GND* : AA4 : : : : 7 :
GND* : AA5 : : : : 7 :
GND* : AA6 : : : : 7 :
GND* : AA7 : : : : 7 :
GND* : AA8 : : : : 7 :
GND* : AA9 : : : : 10 :
GND* : AA10 : : : : 10 :
GND* : AA11 : : : : 7 :
GND* : AA12 : : : : 8 :
GND* : AA13 : : : : 8 :
VREFB8 : AA14 : power : : : 8 :
GND* : AA15 : : : : 8 :
GND* : AA16 : : : : 8 :
GND* : AA17 : : : : 8 :
GND* : AA18 : : : : 8 :
TCK : AA19 : input : : : 8 :
TMS : AA20 : input : : : 8 :
GND : AA21 : gnd : : : :
VCCIO1 : AA22 : power : : 3.3V : 1 :
GND : AB1 : gnd : : : :
nIO_PULLUP : AB2 : : : : 7 :
VCCIO7 : AB3 : power : : 3.3V : 7 :
GND : AB4 : gnd : : : :
GND* : AB5 : : : : 7 :
GND* : AB6 : : : : 7 :
GND* : AB7 : : : : 7 :
GND* : AB8 : : : : 7 :
GND : AB9 : gnd : : : :
GND* : AB10 : : : : 10 :
VCCIO7 : AB11 : power : : 3.3V : 7 :
VCCIO8 : AB12 : power : : 3.3V : 8 :
GND* : AB13 : : : : 8 :
GND : AB14 : gnd : : : :
GND* : AB15 : : : : 8 :
GND* : AB16 : : : : 8 :
GND* : AB17 : : : : 8 :
GND* : AB18 : : : : 8 :
TRST : AB19 : input : : : 8 :
VCCIO8 : AB20 : power : : 3.3V : 8 :
TDI : AB21 : input : : : 8 :
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