; Allow Any Shift Register Size For Recognition                ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
+--------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; half_clk.v                       ; yes             ; User Verilog HDL File  ; E:/lab/half_clk/half_clk.v   ;
+----------------------------------+-----------------+------------------------+------------------------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------------------+--------------+
; Resource                                      ; Usage        ;
+-----------------------------------------------+--------------+
; Estimated ALUTs Used                          ; 1            ;
; Dedicated logic registers                     ; 1            ;
;                                               ;              ;
; Estimated ALUTs Unavailable                   ; 0            ;
;                                               ;              ;
; Total combinational functions                 ; 1            ;
; Combinational ALUT usage by number of inputs  ;              ;
;     -- 7 input functions                      ; 0            ;
;     -- 6 input functions                      ; 0            ;
;     -- 5 input functions                      ; 0            ;
;     -- 4 input functions                      ; 0            ;
;     -- <=3 input functions                    ; 1            ;
;                                               ;              ;
; Combinational ALUTs by mode                   ;              ;
;     -- normal mode                            ; 1            ;
;     -- extended LUT mode                      ; 0            ;
;     -- arithmetic mode                        ; 0            ;
;     -- shared arithmetic mode                 ; 0            ;
;                                               ;              ;
; Estimated ALUT/register pairs used            ; 1            ;
;                                               ;              ;
; Total registers                               ; 1            ;
;     -- Dedicated logic registers              ; 1            ;
;     -- I/O registers                          ; 0            ;
;                                               ;              ;
; Estimated ALMs:  partially or completely used ; 1            ;
;                                               ;              ;
; I/O pins                                      ; 3            ;
; Maximum fan-out node                          ; clk_out~reg0 ;
; Maximum fan-out                               ; 2            ;
; Total fan-out                                 ; 5            ;
; Average fan-out                               ; 1.00         ;
+-----------------------------------------------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |half_clk                  ; 1 (1)             ; 1 (1)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 3    ; 0            ; |half_clk           ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Sat May 16 10:40:06 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off half_clk -c half_clk
Info: Found 1 design units, including 1 entities, in source file half_clk.v
    Info: Found entity 1: half_clk
Info: Elaborating entity "half_clk" for the top level hierarchy
Info: Implemented 4 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 160 megabytes
    Info: Processing ended: Sat May 16 10:40:07 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01