`timescale 1ns/ns`include "./compare.v"module comparetest;reg a,b;wire equal;initialbegin a=0;      b=0;#100 a=0;b=1;#100 a=1;     b=1; #100 a=1;     b=0;#100 $stop;endcompare compare1(.equal(equal),.a(a),.b(b));endmodule