?? tryfunct.tan.rpt
字號:
Classic Timing Analyzer report for tryfunct
Sat May 16 20:23:34 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 95.217 ns ; n[2] ; result[0]~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.358 ns ; result[5]~reg0 ; result[5] ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.728 ns ; reset ; result[7]~reg0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+----------------+----------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S15F484C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-------+-----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-------+-----------------+----------+
; N/A ; None ; 95.217 ns ; n[2] ; result[0]~reg0 ; clk ;
; N/A ; None ; 94.816 ns ; n[1] ; result[0]~reg0 ; clk ;
; N/A ; None ; 94.154 ns ; n[3] ; result[0]~reg0 ; clk ;
; N/A ; None ; 93.896 ns ; n[0] ; result[0]~reg0 ; clk ;
; N/A ; None ; 93.563 ns ; n[2] ; result[1]~reg0 ; clk ;
; N/A ; None ; 93.162 ns ; n[1] ; result[1]~reg0 ; clk ;
; N/A ; None ; 92.500 ns ; n[3] ; result[1]~reg0 ; clk ;
; N/A ; None ; 92.242 ns ; n[0] ; result[1]~reg0 ; clk ;
; N/A ; None ; 92.094 ns ; n[2] ; result[2]~reg0 ; clk ;
; N/A ; None ; 91.693 ns ; n[1] ; result[2]~reg0 ; clk ;
; N/A ; None ; 91.031 ns ; n[3] ; result[2]~reg0 ; clk ;
; N/A ; None ; 90.773 ns ; n[0] ; result[2]~reg0 ; clk ;
; N/A ; None ; 89.843 ns ; n[2] ; result[3]~reg0 ; clk ;
; N/A ; None ; 89.442 ns ; n[1] ; result[3]~reg0 ; clk ;
; N/A ; None ; 88.780 ns ; n[3] ; result[3]~reg0 ; clk ;
; N/A ; None ; 88.522 ns ; n[0] ; result[3]~reg0 ; clk ;
; N/A ; None ; 88.373 ns ; n[2] ; result[4]~reg0 ; clk ;
; N/A ; None ; 87.972 ns ; n[1] ; result[4]~reg0 ; clk ;
; N/A ; None ; 87.310 ns ; n[3] ; result[4]~reg0 ; clk ;
; N/A ; None ; 87.052 ns ; n[0] ; result[4]~reg0 ; clk ;
; N/A ; None ; 86.962 ns ; n[2] ; result[5]~reg0 ; clk ;
; N/A ; None ; 86.561 ns ; n[1] ; result[5]~reg0 ; clk ;
; N/A ; None ; 85.899 ns ; n[3] ; result[5]~reg0 ; clk ;
; N/A ; None ; 85.641 ns ; n[0] ; result[5]~reg0 ; clk ;
; N/A ; None ; 85.217 ns ; n[2] ; result[6]~reg0 ; clk ;
; N/A ; None ; 84.816 ns ; n[1] ; result[6]~reg0 ; clk ;
; N/A ; None ; 84.154 ns ; n[3] ; result[6]~reg0 ; clk ;
; N/A ; None ; 83.896 ns ; n[0] ; result[6]~reg0 ; clk ;
; N/A ; None ; 83.412 ns ; n[2] ; result[7]~reg0 ; clk ;
; N/A ; None ; 83.011 ns ; n[1] ; result[7]~reg0 ; clk ;
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