{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 18 10:32:04 2009 " "Info: Processing started: Mon May 18 10:32:04 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seqdet -c seqdet " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seqdet -c seqdet" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "seqdet.v(13) " "Warning (10268): Verilog HDL information at seqdet.v(13): always construct contains both blocking and non-blocking assignments" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seqdet.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seqdet.v" { { "Info" "ISGN_ENTITY_NAME" "1 seqdet " "Info: Found entity 1: seqdet" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seqdet " "Info: Elaborating entity \"seqdet\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 seqdet.v(12) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(12): truncated value with size 32 to match size of target (1)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(16) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(16): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(22) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(22): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(26) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(26): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(30) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(30): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(34) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(34): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(38) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(38): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(42) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(42): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(46) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(46): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(50) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(50): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(54) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(54): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(58) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(58): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(62) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(62): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(66) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(66): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(70) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(70): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 seqdet.v(72) " "Warning (10230): Verilog HDL assignment warning at seqdet.v(72): truncated value with size 32 to match size of target (3)" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lab/seqdet.v/seqdet.map.smsg " "Info: Generated suppressed messages file E:/lab/seqdet.v/seqdet.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Info: Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Info: Implemented 4 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Peak virtual memory: 165 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 18 10:32:06 2009 " "Info: Processing ended: Mon May 18 10:32:06 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}