?? seqdet.tan.rpt
字號:
Classic Timing Analyzer report for seqdet
Mon May 18 10:32:17 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.387 ns ; rst ; state[1]~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.500 ns ; state[0]~reg0 ; z ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 8.469 ns ; x ; z ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.797 ns ; x ; state[2]~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[0]~reg0 ; state[1]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S15F484C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[0]~reg0 ; state[1]~reg0 ; clk ; clk ; None ; None ; 0.730 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[0]~reg0 ; state[2]~reg0 ; clk ; clk ; None ; None ; 0.642 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[2]~reg0 ; state[0]~reg0 ; clk ; clk ; None ; None ; 0.638 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[1]~reg0 ; state[0]~reg0 ; clk ; clk ; None ; None ; 0.581 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[1]~reg0 ; state[2]~reg0 ; clk ; clk ; None ; None ; 0.580 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[0]~reg0 ; state[0]~reg0 ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[2]~reg0 ; state[2]~reg0 ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[1]~reg0 ; state[1]~reg0 ; clk ; clk ; None ; None ; 0.488 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; state[2]~reg0 ; state[1]~reg0 ; clk ; clk ; None ; None ; 0.423 ns ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+---------------+----------+
; N/A ; None ; 3.387 ns ; rst ; state[0]~reg0 ; clk ;
; N/A ; None ; 3.387 ns ; rst ; state[2]~reg0 ; clk ;
; N/A ; None ; 3.387 ns ; rst ; state[1]~reg0 ; clk ;
; N/A ; None ; 3.037 ns ; x ; state[0]~reg0 ; clk ;
; N/A ; None ; 3.037 ns ; x ; state[1]~reg0 ; clk ;
; N/A ; None ; 3.036 ns ; x ; state[2]~reg0 ; clk ;
+-------+--------------+------------+------+---------------+----------+
+---------------------------------------------------------------------------+
; tco ;
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