?? fdivision.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "F10M register j\[0\] register j\[4\] 495.54 MHz 2.018 ns Internal " "Info: Clock \"F10M\" has Internal fmax of 495.54 MHz between source register \"j\[0\]\" and destination register \"j\[4\]\" (period= 2.018 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.834 ns + Longest register register " "Info: + Longest register to register delay is 1.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns j\[0\] 1 REG LCFF_X15_Y15_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 3; REG Node = 'j\[0\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { j[0] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.355 ns) + CELL(0.366 ns) 0.721 ns Equal0~103 2 COMB LCCOMB_X15_Y15_N20 1 " "Info: 2: + IC(0.355 ns) + CELL(0.366 ns) = 0.721 ns; Loc. = LCCOMB_X15_Y15_N20; Fanout = 1; COMB Node = 'Equal0~103'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.721 ns" { j[0] Equal0~103 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.195 ns) + CELL(0.053 ns) 0.969 ns Equal0~104 3 COMB LCCOMB_X15_Y15_N16 2 " "Info: 3: + IC(0.195 ns) + CELL(0.053 ns) = 0.969 ns; Loc. = LCCOMB_X15_Y15_N16; Fanout = 2; COMB Node = 'Equal0~104'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.248 ns" { Equal0~103 Equal0~104 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.202 ns) + CELL(0.053 ns) 1.224 ns j\[1\]~49 4 COMB LCCOMB_X15_Y15_N22 8 " "Info: 4: + IC(0.202 ns) + CELL(0.053 ns) = 1.224 ns; Loc. = LCCOMB_X15_Y15_N22; Fanout = 8; COMB Node = 'j\[1\]~49'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.255 ns" { Equal0~104 j[1]~49 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 1.834 ns j\[4\] 5 REG LCFF_X15_Y15_N9 3 " "Info: 5: + IC(0.213 ns) + CELL(0.397 ns) = 1.834 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { j[1]~49 j[4] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.869 ns ( 47.38 % ) " "Info: Total cell delay = 0.869 ns ( 47.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.965 ns ( 52.62 % ) " "Info: Total interconnect delay = 0.965 ns ( 52.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.834 ns" { j[0] Equal0~103 Equal0~104 j[1]~49 j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.834 ns" { j[0] {} Equal0~103 {} Equal0~104 {} j[1]~49 {} j[4] {} } { 0.000ns 0.355ns 0.195ns 0.202ns 0.213ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F10M destination 2.461 ns + Shortest register " "Info: + Shortest clock path from clock \"F10M\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns F10M 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F10M } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns F10M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { F10M F10M~clkctrl } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns j\[4\] 3 REG LCFF_X15_Y15_N9 3 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { F10M~clkctrl j[4] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[4] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F10M source 2.461 ns - Longest register " "Info: - Longest clock path from clock \"F10M\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns F10M 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F10M } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns F10M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { F10M F10M~clkctrl } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns j\[0\] 3 REG LCFF_X15_Y15_N1 3 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 3; REG Node = 'j\[0\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { F10M~clkctrl j[0] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[0] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[4] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[0] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.834 ns" { j[0] Equal0~103 Equal0~104 j[1]~49 j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.834 ns" { j[0] {} Equal0~103 {} Equal0~104 {} j[1]~49 {} j[4] {} } { 0.000ns 0.355ns 0.195ns 0.202ns 0.213ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.397ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[4] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[0] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "j\[4\] RESET F10M 3.375 ns register " "Info: tsu for register \"j\[4\]\" (data pin = \"RESET\", clock pin = \"F10M\") is 3.375 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.746 ns + Longest pin register " "Info: + Longest pin to register delay is 5.746 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns RESET 1 PIN PIN_H12 2 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 2; PIN Node = 'RESET'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.101 ns) + CELL(0.228 ns) 5.136 ns j\[1\]~49 2 COMB LCCOMB_X15_Y15_N22 8 " "Info: 2: + IC(4.101 ns) + CELL(0.228 ns) = 5.136 ns; Loc. = LCCOMB_X15_Y15_N22; Fanout = 8; COMB Node = 'j\[1\]~49'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.329 ns" { RESET j[1]~49 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 5.746 ns j\[4\] 3 REG LCFF_X15_Y15_N9 3 " "Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.746 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { j[1]~49 j[4] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.432 ns ( 24.92 % ) " "Info: Total cell delay = 1.432 ns ( 24.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.314 ns ( 75.08 % ) " "Info: Total interconnect delay = 4.314 ns ( 75.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.746 ns" { RESET j[1]~49 j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.746 ns" { RESET {} RESET~combout {} j[1]~49 {} j[4] {} } { 0.000ns 0.000ns 4.101ns 0.213ns } { 0.000ns 0.807ns 0.228ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F10M destination 2.461 ns - Shortest register " "Info: - Shortest clock path from clock \"F10M\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns F10M 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F10M } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns F10M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { F10M F10M~clkctrl } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns j\[4\] 3 REG LCFF_X15_Y15_N9 3 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { F10M~clkctrl j[4] } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[4] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.746 ns" { RESET j[1]~49 j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.746 ns" { RESET {} RESET~combout {} j[1]~49 {} j[4] {} } { 0.000ns 0.000ns 4.101ns 0.213ns } { 0.000ns 0.807ns 0.228ns 0.397ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl j[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} j[4] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "F10M F500K F500K~reg0 5.980 ns register " "Info: tco from clock \"F10M\" to destination pin \"F500K\" through register \"F500K~reg0\" is 5.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F10M source 2.461 ns + Longest register " "Info: + Longest clock path from clock \"F10M\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns F10M 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F10M } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns F10M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { F10M F10M~clkctrl } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns F500K~reg0 3 REG LCFF_X15_Y15_N19 2 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} F500K~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.425 ns + Longest register pin " "Info: + Longest register to pin delay is 3.425 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns F500K~reg0 1 REG LCFF_X15_Y15_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F500K~reg0 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.463 ns) + CELL(1.962 ns) 3.425 ns F500K 2 PIN PIN_Y13 0 " "Info: 2: + IC(1.463 ns) + CELL(1.962 ns) = 3.425 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'F500K'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { F500K~reg0 F500K } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.962 ns ( 57.28 % ) " "Info: Total cell delay = 1.962 ns ( 57.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.463 ns ( 42.72 % ) " "Info: Total interconnect delay = 1.463 ns ( 42.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { F500K~reg0 F500K } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.425 ns" { F500K~reg0 {} F500K {} } { 0.000ns 1.463ns } { 0.000ns 1.962ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} F500K~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { F500K~reg0 F500K } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.425 ns" { F500K~reg0 {} F500K {} } { 0.000ns 1.463ns } { 0.000ns 1.962ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "F500K~reg0 RESET F10M -2.682 ns register " "Info: th for register \"F500K~reg0\" (data pin = \"RESET\", clock pin = \"F10M\") is -2.682 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F10M destination 2.461 ns + Longest register " "Info: + Longest clock path from clock \"F10M\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns F10M 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { F10M } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns F10M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { F10M F10M~clkctrl } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns F500K~reg0 3 REG LCFF_X15_Y15_N19 2 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} F500K~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.292 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns RESET 1 PIN PIN_H12 2 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 2; PIN Node = 'RESET'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.102 ns) + CELL(0.228 ns) 5.137 ns F500K~84 2 COMB LCCOMB_X15_Y15_N18 1 " "Info: 2: + IC(4.102 ns) + CELL(0.228 ns) = 5.137 ns; Loc. = LCCOMB_X15_Y15_N18; Fanout = 1; COMB Node = 'F500K~84'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.330 ns" { RESET F500K~84 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.292 ns F500K~reg0 3 REG LCFF_X15_Y15_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.292 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { F500K~84 F500K~reg0 } "NODE_NAME" } } { "fdivision.v" "" { Text "E:/lab/fdivision.v/fdivision.v" 6 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.190 ns ( 22.49 % ) " "Info: Total cell delay = 1.190 ns ( 22.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.102 ns ( 77.51 % ) " "Info: Total interconnect delay = 4.102 ns ( 77.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { RESET F500K~84 F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { RESET {} RESET~combout {} F500K~84 {} F500K~reg0 {} } { 0.000ns 0.000ns 4.102ns 0.000ns } { 0.000ns 0.807ns 0.228ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { F10M F10M~clkctrl F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { F10M {} F10M~combout {} F10M~clkctrl {} F500K~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.292 ns" { RESET F500K~84 F500K~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.292 ns" { RESET {} RESET~combout {} F500K~84 {} F500K~reg0 {} } { 0.000ns 0.000ns 4.102ns 0.000ns } { 0.000ns 0.807ns 0.228ns 0.155ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
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