LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY enc32 IS
   PORT( 
         data_in          : in std_logic;
         enclk            : in std_logic;
         uniquebit        : in std_logic;
         den              : in std_logic;
         t_data_in        : out std_logic;
         t_data0          : out std_logic;
         t_buf_we         : out std_logic;
         t_buf_rden       : out std_logic;
         t_count1         : out std_logic_vector(4 downto 0);
         tuniquebit            : out std_logic;
         t_rpar           : out std_logic;
         t_xencout        : out std_logic;
         t_reg            : out std_logic_vector(4 downto 0);
         t_count2         : out integer range 0 to 22;
         t_bufwad         : out std_logic_vector(4 downto 0);
         t_count3         : out std_logic_vector(4 downto 0);
         t_count4         : out integer range 0 to 21;
         t_bufq           : out std_logic_vector (5 downto 0);
         t_xdata0         : out std_logic;
         t_ydata0         : out std_logic;
         t_buf_din        : out std_logic_vector(5 downto 0);
         t_uniquebit_temp : out std_logic;
         t_encout         : out std_logic;
         t_raddr          : out std_logic_vector(4 downto 0)
         --dout             : out std_logic
         --data0            : out std_logic
	   );
END enc32;

ARCHITECTURE rtl OF enc32 IS

signal count1                                           : std_logic_vector(4 downto 0);
signal count2,count2temp0,count2temp1,count2temp2       : integer range 0 to 22;
signal count2temp3,count2temp4                          : integer range 0 to 22;

signal count3                                           : std_logic_vector(4 downto 0);
signal count4,count4temp0,count4temp1,count4temp2       : integer range 0 to 21;
signal data0,data1,data2,data3,data4,data5              : std_logic;
signal buf_rden,buf_rden0                               : std_logic;
signal buf_we,buf_we_temp0,buf_we_temp1,buf_we_temp2    : std_logic;

signal buf_rdentemp                                     : std_logic;

signal xdata0,ydata0                                               : std_logic;
signal rreg                                                        : std_logic_vector(4 downto 0);
signal rpar                                                        : std_logic;
signal xencout                                                     : std_logic;
signal buf_wadtemp0,buf_wadtemp1,buf_wadtemp2,buf_wad              : std_logic_vector(4 downto 0);
signal buf_wadtemp3                                                : std_logic_vector(4 downto 0);

signal raddr                                                       : std_logic_vector(4 downto 0);

signal uniquebit_temp0,uniquebit_temp1,uniquebit_temp2              : std_logic;
signal uniquebit_temp3,uniquebit_temp4,uniquebit_temp5              : std_logic;
--signal uniquebit_temp6                                              : std_logic;

signal buf_din,bufq,bufqtemp                                       : std_logic_vector(5 downto 0);
signal encout                                                      : std_logic;
 
component ybuf IS
 port
	(
		data		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
END component;


begin

process(enclk)
begin
   if enclk'event and enclk='1' then
      data0<=data_in;
      data1<=data0;
      data2<=data1;
      data3<=data2;
      data4<=data3;
      data5<=data4;

      uniquebit_temp0<=uniquebit;
      uniquebit_temp1<=uniquebit_temp0;
      uniquebit_temp2<=uniquebit_temp1;
      uniquebit_temp3<=uniquebit_temp2;
      uniquebit_temp4<=uniquebit_temp3;
      uniquebit_temp5<=uniquebit_temp4;
      --uniquebit_temp6<=uniquebit_temp5;


   end if;
end process;

process(enclk,uniquebit)
begin
   if enclk'event and enclk='1' then
      if uniquebit='1' then
         count1<="10101";
      else
         case count1 is
           when "10101"=>count1<="00000";
           when others=>count1<=count1+"00001";
         end case;
      end if;
   end if;
end process;

process(enclk)
begin
  if enclk'event and enclk='1' then
     case count1 is
          when "10101"=>buf_rden0<='1';
          when "01111"=>buf_rden0<='0';
          when others=>null;
     end case;
    buf_rden<=buf_rden0 and (not uniquebit_temp0);
    buf_rdentemp<=buf_rden;


    raddr<=count1;
  end if; 
end process;



process(enclk)--count4)
begin
    if enclk'event and enclk='1' then
      case count4temp1 is
        when 0 to 20=>buf_we_temp0<=buf_rdentemp;
        when others =>buf_we_temp0<='0'; 
      end case;
      buf_we_temp1<=buf_we_temp0;

      buf_wadtemp0<=count1;
      buf_wadtemp1<=buf_wadtemp0;
      buf_wadtemp1<=buf_wadtemp0;
      buf_wadtemp2<=buf_wadtemp1;
      buf_wadtemp3<=buf_wadtemp2;

      buf_wad<=buf_wadtemp3;
      buf_we<=buf_we_temp1;
    end if;

end process;


count2temp0<=conv_integer(count1);
process(enclk)
begin
   if enclk'event and enclk='1' then
      count2temp1<=count2temp0;
      count2temp2<=count2temp1;
      count2temp3<=count2temp2;

      count2<=count2temp3;
   end if;
end process;

process(enclk)
begin
  if enclk'event and enclk='1' then
     case count4temp2 is
         when 0 to 15=>xdata0<=data3;
         when 16     =>xdata0<=bufqtemp(5);
         when 17     =>xdata0<=bufqtemp(4);
         when 18     =>xdata0<=bufqtemp(3);
         when 19     =>xdata0<=bufqtemp(2);
         when 20     =>xdata0<=bufqtemp(1);
         when 21     =>xdata0<=bufqtemp(0);
         when others=>null; 
     end case;
   end if;
end process;

process(enclk)
variable rtemp:  std_logic;
begin
   if enclk'event and enclk='1' then		
       case count2 is
            when 0      => rtemp:= xdata0;		
				           rreg(4)<= '0';--rreg(3);
						   rreg(3)<= '0';--rreg(2);
				           rreg(2)<= rtemp;--rreg(1) xor rtemp;
						   rreg(1)<= '0';--rreg(0);
					       rreg(0)<= rtemp;
            when 1 to 15=> rtemp:= rreg(4) xor xdata0;		
				           rreg(4)<= rreg(3);
						   rreg(3)<= rreg(2);
				           rreg(2)<= rreg(1) xor rtemp;
						   rreg(1)<= rreg(0);
					       rreg(0)<= rtemp;
			when 16 to 20 =>for i in 0 to 3 loop
					 	      rreg(i+1)<=rreg(i);	
					        end loop;
						      rreg(0)<='0';
			when others=> null;
        end case;
    end if;
end process;

process(enclk)
begin	  
if enclk'event and enclk='1' then	
	 case count2 is
	      when 0       => rpar<=xdata0;
	      when 1  to 15=> rpar<=rpar xor xdata0;
	      when 16 to 20=> rpar<=rpar xor rreg(4);
	      when others =>null;
	 end case;
 end if;
end process;

process(enclk)
begin
   if enclk'event and enclk='1' then	
      case count2 is
		  when 0  to 15=>  xencout<=xdata0;
		  when 16 to 20=>  xencout<=rreg(4);
		  when 21      =>  xencout<=rpar;
          when others=> null;
	  end case;
    end if;     
end process;
-------------------------------------------------------------

process(enclk)
begin
if enclk'event and enclk='1' then--10_8
   if uniquebit='1' then
       count3<="10101";
   else
       if count1="00000" then
         case count3 is
            when "10101"=>count3<="00000";
            when others=>count3<=count3+"00001";
         end case;
       end if;
    end if;
end if;
end process;

count4temp0<=conv_integer(count3);
process(enclk)
begin
   if enclk'event and enclk='1' then
      count4temp1<=count4temp0;
      count4temp2<=count4temp1; 
 
      count4<=count4temp2;
   end if;
end process;

ybuf_inst: ybuf port map (
		data     =>buf_din,
		wren     =>buf_we,
		wraddress=>buf_wad,
		rdaddress=>raddr,
		rden     =>buf_rden,
		clock    =>enclk,
		q        =>bufqtemp
		);
		

process(enclk)
begin
   if enclk'event and enclk='1' then
     ydata0<=data3;
     bufq<=bufqtemp;
   end if;
end process;

process(enclk)
variable ytemp:  std_logic;
begin
if enclk'event and enclk='1' then
   --if uniquebit_temp4='1' then
       --buf_din(5 downto 1)<="00000";
  -- else
      case count4 is
          when 0 =>ytemp:= ydata0;
				   buf_din(5)<= '0';
				   buf_din(4)<= '0';
				   buf_din(3)<= ytemp;
				   buf_din(2)<='0';
				   buf_din(1)<= ytemp;
          when 1 to 15=>ytemp:= bufq(5) xor ydata0;		
				        buf_din(5)<= bufq(4);
					    buf_din(4)<= bufq(3);
				        buf_din(3)<= bufq(2) xor ytemp;
				        buf_din(2)<= bufq(1);
					    buf_din(1)<= ytemp;
		  when 16 to 20=>buf_din(5 downto 1)<=bufq(5 downto 1);
          when 21      =>buf_din(5 downto 1)<="00000";
		  when others=>null;		
      end case;
    --end if;   
   end if;
end process;

process(enclk)
begin
  if enclk'event and enclk='1' then
       case count4  is
	             when 0      => buf_din(0)<=ydata0;
	             when 1 to 15=> buf_din(0)<=bufq(0) xor ydata0;
	             when 16     => buf_din(0)<=bufq(0) xor bufq(5);
	             when 17     => buf_din(0)<=bufq(0) xor bufq(4);
		         when 18     => buf_din(0)<=bufq(0) xor bufq(3);
	             when 19     => buf_din(0)<=bufq(0) xor bufq(2);
	             when 20     => buf_din(0)<=bufq(0) xor bufq(1);
	             when 21     => buf_din(0)<='0';--bufq(0);
	             when others =>null;
	   end case;
	end if;
end process;
 
process(enclk)
begin
  if enclk'event and enclk='1' then
     case uniquebit_temp5 is
          when '1'=>encout<=data5;
          when '0'=>encout<=xencout;
     end case;
  end if;
end process;
		    
process(enclk)
begin
   if enclk'event and enclk='1' then
      t_data_in<=data_in;
      t_data0<=data2;
      t_buf_we<=buf_we;
      t_buf_rden<=buf_rden;
      t_count1<=count1;
      tuniquebit<=uniquebit_temp3;
      t_rpar<=rpar;
      t_xencout<=xencout;
      t_reg<=rreg;
      t_count2<=count2;
      t_bufwad<=buf_wad;
      t_count3<=count3;
      t_count4<=count4;
      t_bufq<=bufq;
      t_xdata0<=xdata0;
      t_ydata0<=ydata0;
      t_buf_din<=buf_din;
      t_uniquebit_temp<=uniquebit_temp5;
      t_encout<=encout;
      t_raddr<=raddr;
   end if;
end process;


end rtl;