LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY mapena_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic
	   );
END  mapena_shift;

ARCHITECTURE rtl OF mapena_shift IS
signal shift0,shift1,shift2,shift3              : std_logic;
signal temp0,temp1,temp2,temp3,temp4              : std_logic;
signal temp5,temp6,temp7,temp8,temp9              : std_logic;
signal temp10,temp11,temp12,temp13,temp14              : std_logic;
signal temp15,temp16,temp17,temp18,temp19              : std_logic;
signal temp20,temp21,temp22,temp23,temp24              : std_logic;
signal temp25,temp26,temp27,temp28,temp29              : std_logic;
signal t0,t1,t2,t3,t4,t5,t6,t7,t8              : std_logic;
component shift IS
   PORT( clk              : in std_logic;
         input            : in std_logic;
         output           : out std_logic 
	   );
END  component;

begin

s0: shift port map(clk,input,temp0);
s1: shift port map(clk,temp0,temp1);
s2: shift port map(clk,temp1,temp2);
s3: shift port map(clk,temp2,temp3);
s4: shift port map(clk,temp3,temp4);
s5: shift port map(clk,temp4,temp5);
s6: shift port map(clk,temp5,temp6);
s7: shift port map(clk,temp6,temp7);
s8: shift port map(clk,temp7,temp8);
s9: shift port map(clk,temp8,temp9);
s10: shift port map(clk,temp9,temp10);
s11: shift port map(clk,temp10,temp11);
s12: shift port map(clk,temp11,temp12);
s13: shift port map(clk,temp12,temp13);
s14: shift port map(clk,temp13,temp14);
s15: shift port map(clk,temp14,temp15);
s16: shift port map(clk,temp15,temp16);
s17: shift port map(clk,temp16,temp17);
s18: shift port map(clk,temp17,temp18);
s19: shift port map(clk,temp18,temp19);
s20: shift port map(clk,temp19,temp20);
s21: shift port map(clk,temp20,temp21);
s22: shift port map(clk,temp21,temp22);
s23: shift port map(clk,temp22,temp23);
s24: shift port map(clk,temp23,temp24);
s25: shift port map(clk,temp24,temp25);
process(clk)
begin
    if clk'event and clk='1' then
       t0<=temp0;
       t1<=t0;
       t2<=t1;
       t3<=t2;

       output<=temp0;
    end if;
end process;



end rtl;