LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY qpsk_map IS
   PORT( encoded          : in std_logic_vector(0 downto 0);
         clk              : in std_logic;
         clk2x            : in std_logic;
         flag             : in std_logic;
         --outena           : in std_logic; 
         iout             : out std_logic;
         qout             : out std_logic;
         isym             : out std_logic_vector(4 downto 0);
         qsym             : out std_logic_vector(4 downto 0);
         tcnt1            : out std_logic_vector(2 downto 0);
         tcnt2            : out std_logic_vector(1 downto 0);
         encin            : out std_logic_vector(0 downto 0)
         --mq               : out std_logic_vector(1 downto 0)
          
	   );
END  qpsk_map;

ARCHITECTURE rtl OF qpsk_map IS
signal cnt1,cnt1_temp              : std_logic_vector(2 downto 0);
signal cnt2,cnt2_temp0,cnt2_temp1  : std_logic_vector(1 downto 0);
--signal mapout_temp                 : std_logic_vector(1 downto 0);
signal ramout                      : std_logic_vector(1 downto 0);
--signal itemp,qtemp                 : std_logic;           
component mapram IS
 PORT
	(
		data		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rdaddress	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
END component;

begin

process(clk2x)
begin
    if clk2x'event and clk2x='1' then
       if flag='1' then
          cnt1<="000";
       else
          cnt1<=cnt1+'1';
       end if;
       cnt1_temp<=cnt1;
       tcnt1<=cnt1_temp;
       encin<=encoded;
    end if;
end process;

process(clk2x)
begin
    if clk2x'event and clk2x='1' then
        cnt2<=cnt1_temp(2 downto 1);
        cnt2_temp0<=cnt2;
        cnt2_temp1<=cnt2_temp0;
        --cnt2_temp2<=cnt2_temp0;
        tcnt2<=cnt2_temp1;
    end if;
end process;

mapram_inst : mapram PORT MAP (
		data	 => encoded,
		wren	 =>'1',
		wraddress	 => cnt1_temp,
		rdaddress	 => cnt2_temp1,
		rden	 =>'1',
		wrclock	 =>clk2x,
		rdclock	 =>clk,
		q	 => ramout
	);



process(clk)
begin
    if clk'event and clk='1' then
       iout<=ramout(0);
       qout<=ramout(1);
       case ramout(0) is
           when '0'=>isym<="01111";
           when '1'=>isym<="10001";
       end case;

       case ramout(1) is
           when '0'=>qsym<="01111";
           when '1'=>qsym<="10001";
       end case;

    end if;
end process;


end rtl;