?? altsyncram_c311.tdf
字號:
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a31 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 15,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a32 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a33 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a34 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a35 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a36 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a37 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a38 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a39 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a40 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 8,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a41 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 9,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a42 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 10,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a43 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 11,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a44 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 12,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a45 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 13,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a46 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "payload_buffer.hex",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
OPERATION_MODE = "single_port",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
PORT_A_BYTE_SIZE = 1,
PORT_A_DATA_OUT_CLEAR = "none",
PORT_A_DATA_OUT_CLOCK = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 8192,
PORT_A_FIRST_BIT_NUMBER = 14,
PORT_A_LAST_ADDRESS = 12287,
PORT_A_LOGICAL_RAM_DEPTH = 16384,
PORT_A_LOGICAL_RAM_WIDTH = 16,
RAM_BLOCK_TYPE = "M4K"
);
ram_block1a47 : cycloneii_ram_block
WITH (
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