--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 4 
SUBDESIGN decode_4oa
( 
	data[1..0]	:	input;
	enable	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode543w[2..0]	: WIRE;
	w_anode556w[2..0]	: WIRE;
	w_anode564w[2..0]	: WIRE;
	w_anode572w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode572w[2..2], w_anode564w[2..2], w_anode556w[2..2], w_anode543w[2..2]);
	w_anode543w[] = ( (w_anode543w[1..1] & (! data_wire[1..1])), (w_anode543w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode556w[] = ( (w_anode556w[1..1] & (! data_wire[1..1])), (w_anode556w[0..0] & data_wire[0..0]), enable_wire);
	w_anode564w[] = ( (w_anode564w[1..1] & data_wire[1..1]), (w_anode564w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode572w[] = ( (w_anode572w[1..1] & data_wire[1..1]), (w_anode572w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE