--lpm_counter DEVICE_FAMILY="Cyclone II" lpm_width=6 aclr clock cnt_en q sclr updown
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
WITH ( 	LUT_MASK,	SUM_LUTC_INPUT) 
RETURNS ( combout, cout);
FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
RETURNS ( regout);

--synthesis_resources = lut 6 reg 6 
SUBDESIGN cntr_rj7
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[5..0]	:	output;
	sclr	:	input;
	updown	:	input;
) 
VARIABLE 
	counter_comb_bita0 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita1 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita2 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita3 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita4 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_comb_bita5 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_reg_bit1a[5..0] : cycloneii_lcell_ff;
	a_val[5..0]	: WIRE;
	aclr_actual	: WIRE;
	clk_en	: NODE;
	data[5..0]	: NODE;
	external_cin	: WIRE;
	s_val[5..0]	: WIRE;
	safe_q[5..0]	: WIRE;
	sload	: NODE;
	sset	: NODE;
	time_to_clear	: WIRE;
	updown_dir	: WIRE;

BEGIN 
	counter_comb_bita[0].cin = external_cin;
	counter_comb_bita[1].cin = counter_comb_bita[0].cout;
	counter_comb_bita[2].cin = counter_comb_bita[1].cout;
	counter_comb_bita[3].cin = counter_comb_bita[2].cout;
	counter_comb_bita[4].cin = counter_comb_bita[3].cout;
	counter_comb_bita[5].cin = counter_comb_bita[4].cout;
	counter_comb_bita[0].dataa = counter_reg_bit1a[0].regout;
	counter_comb_bita[1].dataa = counter_reg_bit1a[1].regout;
	counter_comb_bita[2].dataa = counter_reg_bit1a[2].regout;
	counter_comb_bita[3].dataa = counter_reg_bit1a[3].regout;
	counter_comb_bita[4].dataa = counter_reg_bit1a[4].regout;
	counter_comb_bita[5].dataa = counter_reg_bit1a[5].regout;
	counter_comb_bita[0].datab = updown_dir;
	counter_comb_bita[1].datab = updown_dir;
	counter_comb_bita[2].datab = updown_dir;
	counter_comb_bita[3].datab = updown_dir;
	counter_comb_bita[4].datab = updown_dir;
	counter_comb_bita[5].datab = updown_dir;
	counter_comb_bita[0].datad = B"1";
	counter_comb_bita[1].datad = B"1";
	counter_comb_bita[2].datad = B"1";
	counter_comb_bita[3].datad = B"1";
	counter_comb_bita[4].datad = B"1";
	counter_comb_bita[5].datad = B"1";
	counter_reg_bit1a[].aclr = aclr_actual;
	counter_reg_bit1a[].clk = clock;
	counter_reg_bit1a[0].datain = counter_comb_bita[0].combout;
	counter_reg_bit1a[1].datain = counter_comb_bita[1].combout;
	counter_reg_bit1a[2].datain = counter_comb_bita[2].combout;
	counter_reg_bit1a[3].datain = counter_comb_bita[3].combout;
	counter_reg_bit1a[4].datain = counter_comb_bita[4].combout;
	counter_reg_bit1a[5].datain = counter_comb_bita[5].combout;
	counter_reg_bit1a[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
	counter_reg_bit1a[].sdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
	counter_reg_bit1a[].sload = ((sclr # sset) # sload);
	a_val[] = B"111111";
	aclr_actual = aclr;
	clk_en = VCC;
	data[] = GND;
	external_cin = B"1";
	q[] = safe_q[];
	s_val[] = B"111111";
	safe_q[] = counter_reg_bit1a[].regout;
	sload = GND;
	sset = GND;
	time_to_clear = B"0";
	updown_dir = updown;
END;
--VALID FILE