{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SYS_CLK register rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\] register rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\] 51.9 MHz 19.266 ns Internal " "Info: Clock \"SYS_CLK\" has Internal fmax of 51.9 MHz between source register \"rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\]\" and destination register \"rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\]\" (period= 19.266 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.980 ns + Longest register register " "Info: + Longest register to register delay is 18.980 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\] 1 REG LCFF_X20_Y7_N13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y7_N13; Fanout = 8; REG Node = 'rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.611 ns) + CELL(0.636 ns) 5.247 ns rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~318 2 COMB LCCOMB_X21_Y11_N18 1 " "Info: 2: + IC(4.611 ns) + CELL(0.636 ns) = 5.247 ns; Loc. = LCCOMB_X21_Y11_N18; Fanout = 1; COMB Node = 'rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~318'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "5.247 ns" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1792 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.210 ns) 5.806 ns rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~319 3 COMB LCCOMB_X21_Y11_N24 37 " "Info: 3: + IC(0.349 ns) + CELL(0.210 ns) = 5.806 ns; Loc. = LCCOMB_X21_Y11_N24; Fanout = 37; COMB Node = 'rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_instruction_master_requests_payload_buffer_s1~319'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.559 ns" { rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1792 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.378 ns) 6.529 ns rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|payload_buffer_s1_firsttransfer~82 4 COMB LCCOMB_X21_Y11_N20 2 " "Info: 4: + IC(0.345 ns) + CELL(0.378 ns) = 6.529 ns; Loc. = LCCOMB_X21_Y11_N20; Fanout = 2; COMB Node = 'rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|payload_buffer_s1_firsttransfer~82'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.723 ns" { rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1865 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.636 ns) 8.296 ns rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_data_master_qualified_request_payload_buffer_s1~166 5 COMB LCCOMB_X20_Y8_N24 11 " "Info: 5: + IC(1.131 ns) + CELL(0.636 ns) = 8.296 ns; Loc. = LCCOMB_X20_Y8_N24; Fanout = 11; COMB Node = 'rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|cpu_0_data_master_qualified_request_payload_buffer_s1~166'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.767 ns" { rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1786 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.664 ns) 9.355 ns rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|payload_buffer_s1_grant_vector\[1\]~110 6 COMB LCCOMB_X20_Y8_N10 18 " "Info: 6: + IC(0.395 ns) + CELL(0.664 ns) = 9.355 ns; Loc. = LCCOMB_X20_Y8_N10; Fanout = 18; COMB Node = 'rcIII:inst\|payload_buffer_s1_arbitrator:the_payload_buffer_s1\|payload_buffer_s1_grant_vector\[1\]~110'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.059 ns" { rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1866 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.039 ns) + CELL(0.636 ns) 14.030 ns rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~488 7 COMB LCCOMB_X20_Y6_N26 6 " "Info: 7: + IC(4.039 ns) + CELL(0.636 ns) = 14.030 ns; Loc. = LCCOMB_X20_Y6_N26; Fanout = 6; COMB Node = 'rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~488'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "4.675 ns" { rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 165 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.210 ns) 14.624 ns rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~17 8 COMB LCCOMB_X20_Y6_N30 8 " "Info: 8: + IC(0.384 ns) + CELL(0.210 ns) = 14.624 ns; Loc. = LCCOMB_X20_Y6_N30; Fanout = 8; COMB Node = 'rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~17'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.594 ns" { rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.484 ns) + CELL(0.872 ns) 18.980 ns rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\] 9 REG LCFF_X15_Y8_N19 1 " "Info: 9: + IC(3.484 ns) + CELL(0.872 ns) = 18.980 ns; Loc. = LCFF_X15_Y8_N19; Fanout = 1; REG Node = 'rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "4.356 ns" { rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 164 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.242 ns 22.35 % " "Info: Total cell delay = 4.242 ns ( 22.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.738 ns 77.65 % " "Info: Total interconnect delay = 14.738 ns ( 77.65 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "18.980 ns" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.980 ns" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } { 0.000ns 4.611ns 0.349ns 0.345ns 1.131ns 0.395ns 4.039ns 0.384ns 3.484ns } { 0.000ns 0.636ns 0.210ns 0.378ns 0.636ns 0.664ns 0.636ns 0.210ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.016 ns - Smallest " "Info: - Smallest clock skew is -0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 2.944 ns + Shortest register " "Info: + Shortest clock path from clock \"SYS_CLK\" to destination register is 2.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns SYS_CLK 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'SYS_CLK'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns SYS_CLK~clkctrl 2 COMB CLKCTRL_G14 1543 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 1543; COMB Node = 'SYS_CLK~clkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.117 ns" { SYS_CLK SYS_CLK~clkctrl } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.679 ns) 2.944 ns rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\] 3 REG LCFF_X15_Y8_N19 1 " "Info: 3: + IC(1.048 ns) + CELL(0.679 ns) = 2.944 ns; Loc. = LCFF_X15_Y8_N19; Fanout = 1; REG Node = 'rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[7\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.727 ns" { SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 164 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 60.43 % " "Info: Total cell delay = 1.779 ns ( 60.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns 39.57 % " "Info: Total interconnect delay = 1.165 ns ( 39.57 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.944 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.944 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } { 0.000ns 0.000ns 0.117ns 1.048ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 2.960 ns - Longest register " "Info: - Longest clock path from clock \"SYS_CLK\" to source register is 2.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns SYS_CLK 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'SYS_CLK'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns SYS_CLK~clkctrl 2 COMB CLKCTRL_G14 1543 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 1543; COMB Node = 'SYS_CLK~clkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.117 ns" { SYS_CLK SYS_CLK~clkctrl } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.679 ns) 2.960 ns rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\] 3 REG LCFF_X20_Y7_N13 8 " "Info: 3: + IC(1.064 ns) + CELL(0.679 ns) = 2.960 ns; Loc. = LCFF_X20_Y7_N13; Fanout = 8; REG Node = 'rcIII:inst\|cpu_0:the_cpu_0\|F_pc\[14\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.743 ns" { SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } "NODE_NAME" } "" } } { "cpu_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns 60.10 % " "Info: Total cell delay = 1.779 ns ( 60.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.181 ns 39.90 % " "Info: Total interconnect delay = 1.181 ns ( 39.90 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.960 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.960 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } { 0.000ns 0.000ns 0.117ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.944 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.944 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } { 0.000ns 0.000ns 0.117ns 1.048ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.960 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.960 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } { 0.000ns 0.000ns 0.117ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "cpu_0.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0.v" 521 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 164 -1 0 } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "18.980 ns" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "18.980 ns" { rcIII:inst|cpu_0:the_cpu_0|F_pc[14] rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~318 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_instruction_master_requests_payload_buffer_s1~319 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_firsttransfer~82 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~166 rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|payload_buffer_s1_grant_vector[1]~110 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~488 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~17 rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } { 0.000ns 4.611ns 0.349ns 0.345ns 1.131ns 0.395ns 4.039ns 0.384ns 3.484ns } { 0.000ns 0.636ns 0.210ns 0.378ns 0.636ns 0.664ns 0.636ns 0.210ns 0.872ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.944 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.944 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[7] } { 0.000ns 0.000ns 0.117ns 1.048ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.960 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.960 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|cpu_0:the_cpu_0|F_pc[14] } { 0.000ns 0.000ns 0.117ns 1.064ns } { 0.000ns 1.100ns 0.000ns 0.679ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 97.79 MHz 10.226 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 97.79 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate\" (period= 10.226 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.839 ns + Longest register register " "Info: + Longest register to register delay is 4.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X22_Y17_N21 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y17_N21; Fanout = 10; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.384 ns) + CELL(0.664 ns) 3.048 ns rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53 2 COMB LCCOMB_X23_Y18_N18 4 " "Info: 2: + IC(2.384 ns) + CELL(0.664 ns) = 3.048 ns; Loc. = LCCOMB_X23_Y18_N18; Fanout = 4; COMB Node = 'rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~53'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "3.048 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.210 ns) 3.636 ns rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0 3 COMB LCCOMB_X23_Y18_N8 1 " "Info: 3: + IC(0.378 ns) + CELL(0.210 ns) = 3.636 ns; Loc. = LCCOMB_X23_Y18_N8; Fanout = 1; COMB Node = 'rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.588 ns" { rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.872 ns) 4.839 ns rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 4 REG LCFF_X23_Y18_N3 2 " "Info: 4: + IC(0.331 ns) + CELL(0.872 ns) = 4.839 ns; Loc. = LCFF_X23_Y18_N3; Fanout = 2; REG Node = 'rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.203 ns" { rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.746 ns 36.08 % " "Info: Total cell delay = 1.746 ns ( 36.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.093 ns 63.92 % " "Info: Total interconnect delay = 3.093 ns ( 63.92 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "4.839 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.839 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 2.384ns 0.378ns 0.331ns } { 0.000ns 0.664ns 0.210ns 0.872ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 1.760 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 1.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 96 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 96; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.081 ns) + CELL(0.679 ns) 1.760 ns rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 3 REG LCFF_X23_Y18_N3 2 " "Info: 3: + IC(1.081 ns) + CELL(0.679 ns) = 1.760 ns; Loc. = LCFF_X23_Y18_N3; Fanout = 2; REG Node = 'rcIII:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.760 ns" { altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 38.58 % " "Info: Total cell delay = 0.679 ns ( 38.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.081 ns 61.42 % " "Info: Total interconnect delay = 1.081 ns ( 61.42 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.081ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 1.764 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 1.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 96 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = CLKCTRL_G3; Fanout = 96; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.000 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.679 ns) 1.764 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X22_Y17_N21 10 " "Info: 3: + IC(1.085 ns) + CELL(0.679 ns) = 1.764 ns; Loc. = LCFF_X22_Y17_N21; Fanout = 10; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.764 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.679 ns 38.49 % " "Info: Total cell delay = 0.679 ns ( 38.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.085 ns 61.51 % " "Info: Total interconnect delay = 1.085 ns ( 61.51 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.085ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.081ns } { 0.000ns 0.000ns 0.679ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.085ns } { 0.000ns 0.000ns 0.679ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.310 ns + " "Info: + Micro clock to output delay of source is 0.310 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "4.839 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.839 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~53 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 2.384ns 0.378ns 0.331ns } { 0.000ns 0.664ns 0.210ns 0.872ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.760 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl rcIII:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } { 0.000ns 0.000ns 1.081ns } { 0.000ns 0.000ns 0.679ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.764 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 0.000ns 1.085ns } { 0.000ns 0.000ns 0.679ns } } }  } 0}