{ "Info" "ITDB_TSU_RESULT" "rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\] FLASH_D\[6\] SYS_CLK 3.501 ns register " "Info: tsu for register \"rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\]\" (data pin = \"FLASH_D\[6\]\", clock pin = \"SYS_CLK\") is 3.501 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.132 ns + Longest pin register " "Info: + Longest pin to register delay is 6.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FLASH_D\[6\] 1 PIN PIN_J4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_J4; Fanout = 1; PIN Node = 'FLASH_D\[6\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { FLASH_D[6] } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 144 944 1120 160 "FLASH_D\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.132 ns) 6.132 ns rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\] 2 REG IOC_X0_Y18_N0 8 " "Info: 2: + IC(0.000 ns) + CELL(6.132 ns) = 6.132 ns; Loc. = IOC_X0_Y18_N0; Fanout = 8; REG Node = 'rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "6.132 ns" { FLASH_D[6] rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2404 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.132 ns 100.00 % " "Info: Total cell delay = 6.132 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "6.132 ns" { FLASH_D[6] rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.132 ns" { FLASH_D[6] rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns } { 0.000ns 6.132ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.101 ns + " "Info: + Micro setup delay of destination is 0.101 ns" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2404 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 2.732 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK\" to destination register is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns SYS_CLK 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'SYS_CLK'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns SYS_CLK~clkctrl 2 COMB CLKCTRL_G14 1543 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 1543; COMB Node = 'SYS_CLK~clkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.117 ns" { SYS_CLK SYS_CLK~clkctrl } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.322 ns) 2.732 ns rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\] 3 REG IOC_X0_Y18_N0 8 " "Info: 3: + IC(1.193 ns) + CELL(0.322 ns) = 2.732 ns; Loc. = IOC_X0_Y18_N0; Fanout = 8; REG Node = 'rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|incoming_tri_state_bridge_0_data\[6\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.515 ns" { SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2404 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.422 ns 52.05 % " "Info: Total cell delay = 1.422 ns ( 52.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.310 ns 47.95 % " "Info: Total interconnect delay = 1.310 ns ( 47.95 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.732 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns 0.117ns 1.193ns } { 0.000ns 1.100ns 0.000ns 0.322ns } } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "6.132 ns" { FLASH_D[6] rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.132 ns" { FLASH_D[6] rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns } { 0.000ns 6.132ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.732 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] } { 0.000ns 0.000ns 0.117ns 1.193ns } { 0.000ns 1.100ns 0.000ns 0.322ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYS_CLK FLASH_A\[22\] rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\] 5.469 ns register " "Info: tco from clock \"SYS_CLK\" to destination pin \"FLASH_A\[22\]\" through register \"rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\]\" is 5.469 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 2.758 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to source register is 2.758 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns SYS_CLK 1 CLK PIN_W12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_W12; Fanout = 1; CLK Node = 'SYS_CLK'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.000 ns) 1.217 ns SYS_CLK~clkctrl 2 COMB CLKCTRL_G14 1543 " "Info: 2: + IC(0.117 ns) + CELL(0.000 ns) = 1.217 ns; Loc. = CLKCTRL_G14; Fanout = 1543; COMB Node = 'SYS_CLK~clkctrl'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "0.117 ns" { SYS_CLK SYS_CLK~clkctrl } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.207 ns) + CELL(0.334 ns) 2.758 ns rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\] 3 REG IOC_X0_Y3_N1 1 " "Info: 3: + IC(1.207 ns) + CELL(0.334 ns) = 2.758 ns; Loc. = IOC_X0_Y3_N1; Fanout = 1; REG Node = 'rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "1.541 ns" { SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2408 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.434 ns 51.99 % " "Info: Total cell delay = 1.434 ns ( 51.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns 48.01 % " "Info: Total interconnect delay = 1.324 ns ( 48.01 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.758 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.758 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } { 0.000ns 0.000ns 0.117ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.334ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.187 ns + " "Info: + Micro clock to output delay of source is 0.187 ns" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2408 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.524 ns + Longest register pin " "Info: + Longest register to pin delay is 2.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\] 1 REG IOC_X0_Y3_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = IOC_X0_Y3_N1; Fanout = 1; REG Node = 'rcIII:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_address\[22\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } "NODE_NAME" } "" } } { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2408 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.524 ns) 2.524 ns FLASH_A\[22\] 2 PIN PIN_W4 0 " "Info: 2: + IC(0.000 ns) + CELL(2.524 ns) = 2.524 ns; Loc. = PIN_W4; Fanout = 0; PIN Node = 'FLASH_A\[22\]'" {  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.524 ns" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] FLASH_A[22] } "NODE_NAME" } "" } } { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 128 944 1120 144 "FLASH_A\[23..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.524 ns 100.00 % " "Info: Total cell delay = 2.524 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.524 ns" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] FLASH_A[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.524 ns" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] FLASH_A[22] } { 0.000ns 0.000ns } { 0.000ns 2.524ns } } }  } 0}  } { { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.758 ns" { SYS_CLK SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.758 ns" { SYS_CLK SYS_CLK~combout SYS_CLK~clkctrl rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] } { 0.000ns 0.000ns 0.117ns 1.207ns } { 0.000ns 1.100ns 0.000ns 0.334ns } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "2.524 ns" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] FLASH_A[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.524 ns" { rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[22] FLASH_A[22] } { 0.000ns 0.000ns } { 0.000ns 2.524ns } } }  } 0}