|rcIII_top
FLASH_CE <= rcIII:inst.select_n_to_the_ext_flash
SYS_CLK => rcIII:inst.clk
SYS_CLK => delay_reset_block:inst3.clock_in
RST => delay_reset_block:inst3.reset_n
FLASH_D[0] <= rcIII:inst.tri_state_bridge_0_data[0]
FLASH_D[1] <= rcIII:inst.tri_state_bridge_0_data[1]
FLASH_D[2] <= rcIII:inst.tri_state_bridge_0_data[2]
FLASH_D[3] <= rcIII:inst.tri_state_bridge_0_data[3]
FLASH_D[4] <= rcIII:inst.tri_state_bridge_0_data[4]
FLASH_D[5] <= rcIII:inst.tri_state_bridge_0_data[5]
FLASH_D[6] <= rcIII:inst.tri_state_bridge_0_data[6]
FLASH_D[7] <= rcIII:inst.tri_state_bridge_0_data[7]
FLASH_OE <= rcIII:inst.tri_state_bridge_0_readn
FLASH_RW <= rcIII:inst.write_n_to_the_ext_flash
FLASH_A[0] <= rcIII:inst.tri_state_bridge_0_address[0]
FLASH_A[1] <= rcIII:inst.tri_state_bridge_0_address[1]
FLASH_A[2] <= rcIII:inst.tri_state_bridge_0_address[2]
FLASH_A[3] <= rcIII:inst.tri_state_bridge_0_address[3]
FLASH_A[4] <= rcIII:inst.tri_state_bridge_0_address[4]
FLASH_A[5] <= rcIII:inst.tri_state_bridge_0_address[5]
FLASH_A[6] <= rcIII:inst.tri_state_bridge_0_address[6]
FLASH_A[7] <= rcIII:inst.tri_state_bridge_0_address[7]
FLASH_A[8] <= rcIII:inst.tri_state_bridge_0_address[8]
FLASH_A[9] <= rcIII:inst.tri_state_bridge_0_address[9]
FLASH_A[10] <= rcIII:inst.tri_state_bridge_0_address[10]
FLASH_A[11] <= rcIII:inst.tri_state_bridge_0_address[11]
FLASH_A[12] <= rcIII:inst.tri_state_bridge_0_address[12]
FLASH_A[13] <= rcIII:inst.tri_state_bridge_0_address[13]
FLASH_A[14] <= rcIII:inst.tri_state_bridge_0_address[14]
FLASH_A[15] <= rcIII:inst.tri_state_bridge_0_address[15]
FLASH_A[16] <= rcIII:inst.tri_state_bridge_0_address[16]
FLASH_A[17] <= rcIII:inst.tri_state_bridge_0_address[17]
FLASH_A[18] <= rcIII:inst.tri_state_bridge_0_address[18]
FLASH_A[19] <= rcIII:inst.tri_state_bridge_0_address[19]
FLASH_A[20] <= rcIII:inst.tri_state_bridge_0_address[20]
FLASH_A[21] <= rcIII:inst.tri_state_bridge_0_address[21]
FLASH_A[22] <= rcIII:inst.tri_state_bridge_0_address[22]
FLASH_A[23] <= rcIII:inst.tri_state_bridge_0_address[23]


|rcIII_top|rcIII:inst
clk => clk~0.IN14
reset_n => reset_n_sources.IN1
select_n_to_the_ext_flash <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.select_n_to_the_ext_flash
tri_state_bridge_0_address[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[8] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[9] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[10] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[11] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[12] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[13] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[14] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[15] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[16] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[17] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[18] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[19] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[20] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[21] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[22] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_address[23] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_address
tri_state_bridge_0_data[0] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[1] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[2] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[3] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[4] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[5] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[6] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_data[7] <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_data
tri_state_bridge_0_readn <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.tri_state_bridge_0_readn
write_n_to_the_ext_flash <= tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave.write_n_to_the_ext_flash


|rcIII_top|rcIII:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
clk => registered_cpu_0_data_master_readdata[31].CLK
clk => registered_cpu_0_data_master_readdata[30].CLK
clk => registered_cpu_0_data_master_readdata[29].CLK
clk => registered_cpu_0_data_master_readdata[28].CLK
clk => registered_cpu_0_data_master_readdata[27].CLK
clk => registered_cpu_0_data_master_readdata[26].CLK
clk => registered_cpu_0_data_master_readdata[25].CLK
clk => registered_cpu_0_data_master_readdata[24].CLK
clk => registered_cpu_0_data_master_readdata[23].CLK
clk => registered_cpu_0_data_master_readdata[22].CLK
clk => registered_cpu_0_data_master_readdata[21].CLK
clk => registered_cpu_0_data_master_readdata[20].CLK
clk => registered_cpu_0_data_master_readdata[19].CLK
clk => registered_cpu_0_data_master_readdata[18].CLK
clk => registered_cpu_0_data_master_readdata[17].CLK
clk => registered_cpu_0_data_master_readdata[16].CLK
clk => registered_cpu_0_data_master_readdata[15].CLK
clk => registered_cpu_0_data_master_readdata[14].CLK
clk => registered_cpu_0_data_master_readdata[13].CLK
clk => registered_cpu_0_data_master_readdata[12].CLK
clk => registered_cpu_0_data_master_readdata[11].CLK
clk => registered_cpu_0_data_master_readdata[10].CLK
clk => registered_cpu_0_data_master_readdata[9].CLK
clk => registered_cpu_0_data_master_readdata[8].CLK
clk => registered_cpu_0_data_master_readdata[7].CLK
clk => registered_cpu_0_data_master_readdata[6].CLK
clk => registered_cpu_0_data_master_readdata[5].CLK
clk => registered_cpu_0_data_master_readdata[4].CLK
clk => registered_cpu_0_data_master_readdata[3].CLK
clk => registered_cpu_0_data_master_readdata[2].CLK
clk => registered_cpu_0_data_master_readdata[1].CLK
clk => registered_cpu_0_data_master_readdata[0].CLK
clk => cpu_0_data_master_no_byte_enables_and_last_term~reg0.CLK
clk => dbs_16_reg_segment_0[15].CLK
clk => dbs_16_reg_segment_0[14].CLK
clk => dbs_16_reg_segment_0[13].CLK
clk => dbs_16_reg_segment_0[12].CLK
clk => dbs_16_reg_segment_0[11].CLK
clk => dbs_16_reg_segment_0[10].CLK
clk => dbs_16_reg_segment_0[9].CLK
clk => dbs_16_reg_segment_0[8].CLK
clk => dbs_16_reg_segment_0[7].CLK
clk => dbs_16_reg_segment_0[6].CLK
clk => dbs_16_reg_segment_0[5].CLK
clk => dbs_16_reg_segment_0[4].CLK
clk => dbs_16_reg_segment_0[3].CLK
clk => dbs_16_reg_segment_0[2].CLK
clk => dbs_16_reg_segment_0[1].CLK
clk => dbs_16_reg_segment_0[0].CLK
clk => cpu_0_data_master_dbs_address[1]~reg0.CLK
clk => cpu_0_data_master_dbs_address[0]~reg0.CLK
clk => dbs_8_reg_segment_0[7].CLK
clk => dbs_8_reg_segment_0[6].CLK
clk => dbs_8_reg_segment_0[5].CLK
clk => dbs_8_reg_segment_0[4].CLK
clk => dbs_8_reg_segment_0[3].CLK
clk => dbs_8_reg_segment_0[2].CLK
clk => dbs_8_reg_segment_0[1].CLK
clk => dbs_8_reg_segment_0[0].CLK
clk => dbs_8_reg_segment_1[7].CLK
clk => dbs_8_reg_segment_1[6].CLK
clk => dbs_8_reg_segment_1[5].CLK
clk => dbs_8_reg_segment_1[4].CLK
clk => dbs_8_reg_segment_1[3].CLK
clk => dbs_8_reg_segment_1[2].CLK
clk => dbs_8_reg_segment_1[1].CLK
clk => dbs_8_reg_segment_1[0].CLK
clk => dbs_8_reg_segment_2[7].CLK
clk => dbs_8_reg_segment_2[6].CLK
clk => dbs_8_reg_segment_2[5].CLK
clk => dbs_8_reg_segment_2[4].CLK
clk => dbs_8_reg_segment_2[3].CLK
clk => dbs_8_reg_segment_2[2].CLK
clk => dbs_8_reg_segment_2[1].CLK
clk => dbs_8_reg_segment_2[0].CLK
clk => cpu_0_data_master_waitrequest~reg0.CLK
cpu_0_data_master_address[0] => cpu_0_data_master_address_to_slave[0].DATAIN
cpu_0_data_master_address[1] => cpu_0_data_master_address_to_slave[1].DATAIN
cpu_0_data_master_address[2] => cpu_0_data_master_address_to_slave[2].DATAIN
cpu_0_data_master_address[3] => cpu_0_data_master_address_to_slave[3].DATAIN
cpu_0_data_master_address[4] => cpu_0_data_master_address_to_slave[4].DATAIN
cpu_0_data_master_address[5] => cpu_0_data_master_address_to_slave[5].DATAIN
cpu_0_data_master_address[6] => cpu_0_data_master_address_to_slave[6].DATAIN
cpu_0_data_master_address[7] => cpu_0_data_master_address_to_slave[7].DATAIN
cpu_0_data_master_address[8] => cpu_0_data_master_address_to_slave[8].DATAIN
cpu_0_data_master_address[9] => cpu_0_data_master_address_to_slave[9].DATAIN
cpu_0_data_master_address[10] => cpu_0_data_master_address_to_slave[10].DATAIN
cpu_0_data_master_address[11] => cpu_0_data_master_address_to_slave[11].DATAIN
cpu_0_data_master_address[12] => cpu_0_data_master_address_to_slave[12].DATAIN
cpu_0_data_master_address[13] => cpu_0_data_master_address_to_slave[13].DATAIN
cpu_0_data_master_address[14] => cpu_0_data_master_address_to_slave[14].DATAIN
cpu_0_data_master_address[15] => cpu_0_data_master_address_to_slave[15].DATAIN
cpu_0_data_master_address[16] => cpu_0_data_master_address_to_slave[16].DATAIN