{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 10 23:12:07 2007 " "Info: Processing started: Sat Feb 10 23:12:07 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off rcIII -c rcIII " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off rcIII -c rcIII" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "rcIII EP2C20F484C8 " "Info: Selected device EP2C20F484C8 for design \"rcIII\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C20F484I8 " "Info: Device EP2C20F484I8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C8 " "Info: Device EP2C35F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484I8 " "Info: Device EP2C35F484I8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C8 " "Info: Device EP2C50F484C8 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484I8 " "Info: Device EP2C50F484I8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SYS_CLK (placed in PIN W12 (CLK13, LVDSCLK6p, Input)) " "Info: Automatically promoted node SYS_CLK (placed in PIN W12 (CLK13, LVDSCLK6p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G14 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14" {  } {  } 0}  } { { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 104 232 400 120 "SYS_CLK" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SYS_CLK" } } } } { "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" "" { Report "C:/altera/kits/nios2/components/rcIII/system/db/rcIII_cmp.qrpt" Compiler "rcIII" "UNKNOWN" "V1" "C:/altera/kits/nios2/components/rcIII/system/db/rcIII.quartus_db" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "C:/altera/kits/nios2/components/rcIII/system/rcIII.fld" "" { Floorplan "C:/altera/kits/nios2/components/rcIII/system/rcIII.fld" "" "" { SYS_CLK } "NODE_NAME" } }  } 0}