?? altsyncram_vuo1.tdf
字號:
);
ram_block1a24 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 24,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 24,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a25 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 25,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 25,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a26 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 26,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 26,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a27 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 27,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 27,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a28 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 28,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 28,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a29 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 29,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 29,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a30 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 30,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 30,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a31 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
INIT_FILE = "rf_ram.mif",
INIT_FILE_LAYOUT = "port_a",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "old",
OPERATION_MODE = "bidir_dual_port",
PORT_A_ADDRESS_WIDTH = 5,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 31,
PORT_A_LAST_ADDRESS = 31,
PORT_A_LOGICAL_RAM_DEPTH = 32,
PORT_A_LOGICAL_RAM_WIDTH = 32,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 5,
PORT_B_DATA_IN_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 31,
PORT_B_LAST_ADDRESS = 31,
PORT_B_LOGICAL_RAM_DEPTH = 32,
PORT_B_LOGICAL_RAM_WIDTH = 32,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[4..0] : WIRE;
address_b_wire[4..0] : WIRE;
BEGIN
ram_block1a[31..0].clk0 = clock0;
ram_block1a[31..0].clk1 = clock1;
ram_block1a[31..0].ena0 = clocken0;
ram_block1a[31..0].ena1 = clocken1;
ram_block1a[0].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[1].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[2].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[3].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[4].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[5].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[6].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[7].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[8].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[9].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[10].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[11].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[12].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[13].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[14].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[15].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[16].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[17].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[18].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[19].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[20].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[21].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[22].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[23].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[24].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[25].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[26].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[27].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[28].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[29].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[30].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[31].portaaddr[] = ( address_a_wire[4..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[8..8]);
ram_block1a[9].portadatain[] = ( data_a[9..9]);
ram_block1a[10].portadatain[] = ( data_a[10..10]);
ram_block1a[11].portadatain[] = ( data_a[11..11]);
ram_block1a[12].portadatain[] = ( data_a[12..12]);
ram_block1a[13].portadatain[] = ( data_a[13..13]);
ram_block1a[14].portadatain[] = ( data_a[14..14]);
ram_block1a[15].portadatain[] = ( data_a[15..15]);
ram_block1a[16].portadatain[] = ( data_a[16..16]);
ram_block1a[17].portadatain[] = ( data_a[17..17]);
ram_block1a[18].portadatain[] = ( data_a[18..18]);
ram_block1a[19].portadatain[] = ( data_a[19..19]);
ram_block1a[20].portadatain[] = ( data_a[20..20]);
ram_block1a[21].portadatain[] = ( data_a[21..21]);
ram_block1a[22].portadatain[] = ( data_a[22..22]);
ram_block1a[23].portadatain[] = ( data_a[23..23]);
ram_block1a[24].portadatain[] = ( data_a[24..24]);
ram_block1a[25].portadatain[] = ( data_a[25..25]);
ram_block1a[26].portadatain[] = ( data_a[26..26]);
ram_block1a[27].portadatain[] = ( data_a[27..27]);
ram_block1a[28].portadatain[] = ( data_a[28..28]);
ram_block1a[29].portadatain[] = ( data_a[29..29]);
ram_block1a[30].portadatain[] = ( data_a[30..30]);
ram_block1a[31].portadatain[] = ( data_a[31..31]);
ram_block1a[31..0].portawe = wren_a;
ram_block1a[0].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[1].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[2].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[3].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[4].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[5].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[6].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[7].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[8].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[9].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[10].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[11].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[12].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[13].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[14].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[15].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[16].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[17].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[18].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[19].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[20].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[21].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[22].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[23].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[24].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[25].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[26].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[27].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[28].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[29].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[30].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[31].portbaddr[] = ( address_b_wire[4..0]);
ram_block1a[0].portbdatain[] = ( data_b[0..0]);
ram_block1a[1].portbdatain[] = ( data_b[1..1]);
ram_block1a[2].portbdatain[] = ( data_b[2..2]);
ram_block1a[3].portbdatain[] = ( data_b[3..3]);
ram_block1a[4].portbdatain[] = ( data_b[4..4]);
ram_block1a[5].portbdatain[] = ( data_b[5..5]);
ram_block1a[6].portbdatain[] = ( data_b[6..6]);
ram_block1a[7].portbdatain[] = ( data_b[7..7]);
ram_block1a[8].portbdatain[] = ( data_b[8..8]);
ram_block1a[9].portbdatain[] = ( data_b[9..9]);
ram_block1a[10].portbdatain[] = ( data_b[10..10]);
ram_block1a[11].portbdatain[] = ( data_b[11..11]);
ram_block1a[12].portbdatain[] = ( data_b[12..12]);
ram_block1a[13].portbdatain[] = ( data_b[13..13]);
ram_block1a[14].portbdatain[] = ( data_b[14..14]);
ram_block1a[15].portbdatain[] = ( data_b[15..15]);
ram_block1a[16].portbdatain[] = ( data_b[16..16]);
ram_block1a[17].portbdatain[] = ( data_b[17..17]);
ram_block1a[18].portbdatain[] = ( data_b[18..18]);
ram_block1a[19].portbdatain[] = ( data_b[19..19]);
ram_block1a[20].portbdatain[] = ( data_b[20..20]);
ram_block1a[21].portbdatain[] = ( data_b[21..21]);
ram_block1a[22].portbdatain[] = ( data_b[22..22]);
ram_block1a[23].portbdatain[] = ( data_b[23..23]);
ram_block1a[24].portbdatain[] = ( data_b[24..24]);
ram_block1a[25].portbdatain[] = ( data_b[25..25]);
ram_block1a[26].portbdatain[] = ( data_b[26..26]);
ram_block1a[27].portbdatain[] = ( data_b[27..27]);
ram_block1a[28].portbdatain[] = ( data_b[28..28]);
ram_block1a[29].portbdatain[] = ( data_b[29..29]);
ram_block1a[30].portbdatain[] = ( data_b[30..30]);
ram_block1a[31].portbdatain[] = ( data_b[31..31]);
ram_block1a[31..0].portbrewe = wren_b;
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
q_b[] = ( ram_block1a[31..0].portbdataout[0..0]);
END;
--VALID FILE
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