LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY parity_check IS
	PORT(
			a	: IN	STD_LOGIC_VECTOR(7 DOWNTO 0);
			y	: OUT	STD_LOGIC);
END parity_check;

ARCHITECTURE rtl OF parity_check IS
BEGIN
  PROCESS(a)
Variable tmp:STD_LOGIC;
	Begin
 	tmp:='0';
	For i In 0 To 7 Loop
		tmp:=tmp xor a(i);
	END Loop;
  		y<=tmp;
	END process;
END rtl;