LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4 IS
	PORT(
		a,b,i0,i1,i2,i3	: IN	STD_LOGIC;
					q	: OUT	STD_LOGIC);
END mux4;

ARCHITECTURE mux4_behave OF mux4 IS
  signal sel:STD_LOGIC_VECTOR(0 TO 1);
BEGIN
  PROCESS(a,b,i0,i1,i2,i3)
	begin
 	sel<=a&b;
	case sel IS
	  when "00"=>q<=i0;
	  when "01"=>q<=i1;
      when "10"=>q<=i2;
      when "11"=>q<=i3;
      when others=>q<='Z';
	END CASE;
  END PROCESS;
END mux4_behave;