?? debounce.map.rpt
字號:
Analysis & Synthesis report for debounce
Thu Apr 30 08:55:59 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Inverted Register Statistics
9. Source assignments for lpm_add_sub:Add0|addcore:adder
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Apr 30 08:55:59 2009 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; debounce ;
; Top-level Entity Name ; debounce ;
; Family ; ACEX1K ;
; Total logic elements ; 15 ;
; Total pins ; 4 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+---------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+---------------+---------------+
; Device ; EP1K50QC208-3 ; ;
; Top-level entity name ; debounce ; debounce ;
; Family name ; ACEX1K ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
+----------------------------------------------------------+---------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------------+
; debounce.vhd ; yes ; User VHDL File ; E:/EDA/周愛義/b編ing/按鍵消抖/debounce.vhd ;
; lpm_add_sub.tdf ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal72.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/aglobal72.inc ;
; addcore.tdf ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; Megafunction ; d:/program files/altera/72/quartus/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Total logic elements ; 15 ;
; Total combinational functions ; 10 ;
; -- Total 4-input functions ; 2 ;
; -- Total 3-input functions ; 2 ;
; -- Total 2-input functions ; 2 ;
; -- Total 1-input functions ; 4 ;
; -- Total 0-input functions ; 0 ;
; Total registers ; 6 ;
; Total logic cells in carry chains ; 5 ;
; I/O pins ; 4 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 6 ;
; Total fan-out ; 50 ;
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