/* system.h * * Machine generated for a CPU named "cpu" as defined in: * E:\code\EP1C12\l_standard\stand.ptf * * Generated: 2006-03-23 14:37:46.703 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "stand"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONE"#define RCA_CY1C12_BOARD#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDERR "/dev/jtag_uart"#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "small"#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 0#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 0#define NIOS2_DCACHE_LINE_SIZE_LOG2 0#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x01000020#define NIOS2_RESET_ADDR 0x00000000#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_ONCHIP_MEMORY2#define __ALTERA_AVALON_TIMER#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_SYSID#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __ALTERA_AVALON_PIO#define __REDLOGIC_RTL8019#define __ALTERA_AVALON_LCD_16207/* * ext_flash configuration * */#define EXT_FLASH_NAME "/dev/ext_flash"#define EXT_FLASH_TYPE "altera_avalon_cfi_flash"#define EXT_FLASH_BASE 0x00000000#define EXT_FLASH_SETUP_VALUE 40#define EXT_FLASH_WAIT_VALUE 160#define EXT_FLASH_HOLD_VALUE 40#define EXT_FLASH_TIMING_UNITS "ns"#define EXT_FLASH_UNIT_MULTIPLIER 1#define EXT_FLASH_SIZE 4194304#define EXT_FLASH_CONTENTS_INFO "SIMDIR/ext_flash_lane1.dat 1143076674 SIMDIR/ext_flash.dat 1143076674 SIMDIR/ext_flash_lane0.dat 1143076674"/* * onchip_ram_4K configuration * */#define ONCHIP_RAM_4K_NAME "/dev/onchip_ram_4K"#define ONCHIP_RAM_4K_TYPE "altera_avalon_onchip_memory2"#define ONCHIP_RAM_4K_BASE 0x00400000#define ONCHIP_RAM_4K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0#define ONCHIP_RAM_4K_RAM_BLOCK_TYPE "M4K"#define ONCHIP_RAM_4K_GUI_RAM_BLOCK_TYPE "Automatic"#define ONCHIP_RAM_4K_WRITEABLE 1#define ONCHIP_RAM_4K_DUAL_PORT 0#define ONCHIP_RAM_4K_SIZE_VALUE 4#define ONCHIP_RAM_4K_SIZE_MULTIPLE 1024#define ONCHIP_RAM_4K_CONTENTS_INFO "SIMDIR/onchip_ram_4K.dat 1143076675 QUARTUS_PROJECT_DIR/onchip_ram_4K.hex 1143076675"/* * sys_clk_timer configuration * */#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer"#define SYS_CLK_TIMER_TYPE "altera_avalon_timer"#define SYS_CLK_TIMER_BASE 0x00401880#define SYS_CLK_TIMER_IRQ 0#define SYS_CLK_TIMER_ALWAYS_RUN 0#define SYS_CLK_TIMER_FIXED_PERIOD 0#define SYS_CLK_TIMER_SNAPSHOT 1#define SYS_CLK_TIMER_PERIOD 1#define SYS_CLK_TIMER_PERIOD_UNITS "ms"#define SYS_CLK_TIMER_RESET_OUTPUT 0#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0#define SYS_CLK_TIMER_MULT 0.001#define SYS_CLK_TIMER_FREQ 50000000/* * jtag_uart configuration * */#define JTAG_UART_NAME "/dev/jtag_uart"#define JTAG_UART_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_BASE 0x004018B0#define JTAG_UART_IRQ 1#define JTAG_UART_WRITE_DEPTH 64#define JTAG_UART_READ_DEPTH 64#define JTAG_UART_WRITE_THRESHOLD 8#define JTAG_UART_READ_THRESHOLD 8#define JTAG_UART_READ_CHAR_STREAM ""#define JTAG_UART_SHOWASCII 1#define JTAG_UART_READ_LE 0#define JTAG_UART_WRITE_LE 0/* * sysid configuration * */#define SYSID_NAME "/dev/sysid"#define SYSID_TYPE "altera_avalon_sysid"#define SYSID_BASE 0x004018B8#define SYSID_ID 2312085329u#define SYSID_TIMESTAMP 1143094361u/* * sdram configuration * */#define SDRAM_NAME "/dev/sdram"#define SDRAM_TYPE "altera_avalon_new_sdram_controller"#define SDRAM_BASE 0x01000000#define SDRAM_REGISTER_DATA_IN 1#define SDRAM_SIM_MODEL_BASE 1#define SDRAM_SDRAM_DATA_WIDTH 32#define SDRAM_SDRAM_ADDR_WIDTH 12#define SDRAM_SDRAM_ROW_WIDTH 12#define SDRAM_SDRAM_COL_WIDTH 8#define SDRAM_SDRAM_NUM_CHIPSELECTS 1#define SDRAM_SDRAM_NUM_BANKS 4#define SDRAM_REFRESH_PERIOD 15.625#define SDRAM_POWERUP_DELAY 100#define SDRAM_CAS_LATENCY 3#define SDRAM_T_RFC 70#define SDRAM_T_RP 20#define SDRAM_T_MRD 3#define SDRAM_T_RCD 20#define SDRAM_T_AC 5.5#define SDRAM_T_WR 14#define SDRAM_INIT_REFRESH_COMMANDS 2#define SDRAM_INIT_NOP_DELAY 0#define SDRAM_SHARED_DATA 0#define SDRAM_STARVATION_INDICATOR 0#define SDRAM_TRISTATE_BRIDGE_SLAVE ""#define SDRAM_IS_INITIALIZED 1#define SDRAM_SDRAM_BANK_WIDTH 2#define SDRAM_CONTENTS_INFO "SIMDIR/sdram.dat 1143076728"/* * ext_bus configuration * */#define EXT_BUS_NAME "/dev/ext_bus"#define EXT_BUS_TYPE "altera_avalon_tri_state_bridge"/* * E_RST configuration * */#define E_RST_NAME "/dev/E_RST"#define E_RST_TYPE "altera_avalon_pio"#define E_RST_BASE 0x004018A0#define E_RST_DO_TEST_BENCH_WIRING 0#define E_RST_DRIVEN_SIM_VALUE 0x0000#define E_RST_HAS_TRI 0#define E_RST_HAS_OUT 1#define E_RST_HAS_IN 0#define E_RST_CAPTURE 0#define E_RST_EDGE_TYPE "NONE"#define E_RST_IRQ_TYPE "NONE"#define E_RST_FREQ 50000000/* * redlogic_rtl8019_0 configuration * */#define REDLOGIC_RTL8019_0_NAME "/dev/redlogic_rtl8019_0"#define REDLOGIC_RTL8019_0_TYPE "redlogic_rtl8019"#define REDLOGIC_RTL8019_0_BASE 0x00401800#define REDLOGIC_RTL8019_0_IRQ 2/* * lcd configuration * */#define LCD_NAME "/dev/lcd"#define LCD_TYPE "altera_avalon_lcd_16207"#define LCD_BASE 0x004018C0/* * MicroC/OS-II configuration * */#define ALT_MAX_FD 32#define OS_MAX_TASKS 10#define OS_LOWEST_PRIO 20#define OS_FLAG_EN 1#define OS_THREAD_SAFE_NEWLIB 1#define OS_MUTEX_EN 1#define OS_SEM_EN 1#define OS_MBOX_EN 1#define OS_Q_EN 1#define OS_MEM_EN 1#define OS_FLAG_WAIT_CLR_EN 1#define OS_FLAG_ACCEPT_EN 1#define OS_FLAG_DEL_EN 1#define OS_FLAG_QUERY_EN 1#define OS_FLAG_NAME_SIZE 32#define OS_MAX_FLAGS 20#define OS_MUTEX_ACCEPT_EN 1#define OS_MUTEX_DEL_EN 1#define OS_MUTEX_QUERY_EN 1#define OS_SEM_ACCEPT_EN 1#define OS_SEM_SET_EN 1#define OS_SEM_DEL_EN 1#define OS_SEM_QUERY_EN 1#define OS_MBOX_ACCEPT_EN 1#define OS_MBOX_DEL_EN 1#define OS_MBOX_POST_EN 1#define OS_MBOX_POST_OPT_EN 1#define OS_MBOX_QUERY_EN 1#define OS_Q_ACCEPT_EN 1#define OS_Q_DEL_EN 1#define OS_Q_FLUSH_EN 1#define OS_Q_POST_EN 1#define OS_Q_POST_FRONT_EN 1#define OS_Q_POST_OPT_EN 1#define OS_Q_QUERY_EN 1#define OS_MAX_QS 20#define OS_MEM_QUERY_EN 1#define OS_MEM_NAME_SIZE 32#define OS_MAX_MEM_PART 60#define OS_ARG_CHK_EN 1#define OS_CPU_HOOKS_EN 1#define OS_DEBUG_EN 1#define OS_SCHED_LOCK_EN 1#define OS_TASK_STAT_EN 1#define OS_TASK_STAT_STK_CHK_EN 1#define OS_TICK_STEP_EN 1#define OS_EVENT_NAME_SIZE 32#define OS_MAX_EVENTS 60#define OS_TASK_IDLE_STK_SIZE 512#define OS_TASK_STAT_STK_SIZE 512#define OS_TASK_CHANGE_PRIO_EN 1#define OS_TASK_CREATE_EN 1#define OS_TASK_CREATE_EXT_EN 1#define OS_TASK_DEL_EN 1#define OS_TASK_NAME_SIZE 32#define OS_TASK_PROFILE_EN 1#define OS_TASK_QUERY_EN 1#define OS_TASK_SUSPEND_EN 1#define OS_TASK_SW_HOOK_EN 1#define OS_TIME_TICK_HOOK_EN 1#define OS_TIME_GET_SET_EN 1#define OS_TIME_DLY_RESUME_EN 1#define OS_TIME_DLY_HMSM_EN 1#define ALT_SYS_CLK SYS_CLK_TIMER#define ALT_TIMESTAMP_CLK none/* * Lightweight TCP/IP Stack configuration * */#define MEM_SIZE 32768#define MEMP_NUM_PBUF 32#define MEMP_NUM_NETBUF 32#define MEMP_NUM_UDP_PCB 8#define MEMP_NUM_TCP_PCB 8#define MEMP_NUM_TCP_PCB_LISTEN 2#define MEMP_NUM_API_MSG 32#define MEMP_NUM_TCPIP_MSG 32#define PBUF_POOL_SIZE 16#define PBUF_POOL_BUFSIZE 1536#define ARP_TABLE_SIZE 10#define IP_FORWARD 0#define ICMP_TTL 255#define LWIP_DHCP 1#define DHCP_DOES_ARP_CHECK 1#define LWIP_UDP 1#define LWIP_TCP 1#define TCP_WND 2048#define TCP_MAXRTX 4#define TCP_SYNMAXRTX 4#define TCP_MSS 1476#define TCP_SND_BUF 32768#define LWIP_STATS 0#define LWIP_STACK_SIZE 2048#define LWIP_DEFAULT_IF "lan91c111"/* * Devices associated with code sections. * */#define ALT_TEXT_DEVICE       SDRAM#define ALT_RODATA_DEVICE     SDRAM#define ALT_RWDATA_DEVICE     SDRAM#define ALT_EXCEPTIONS_DEVICE SDRAM#define ALT_RESET_DEVICE      EXT_FLASH#endif /* __SYSTEM_H_ */