{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.399 ns register register " "Info: Estimated most critical path is register to register delay of 4.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\flag1:Q\[7\] 1 REG LAB_X2_Y17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y17; Fanout = 4; REG Node = '\\flag1:Q\[7\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { \flag1:Q[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.114 ns) 1.411 ns Equal0~83 2 COMB LAB_X2_Y18 2 " "Info: 2: + IC(1.297 ns) + CELL(0.114 ns) = 1.411 ns; Loc. = LAB_X2_Y18; Fanout = 2; COMB Node = 'Equal0~83'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.411 ns" { \flag1:Q[7] Equal0~83 } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.043 ns) + CELL(0.292 ns) 2.746 ns Equal0~84 3 COMB LAB_X2_Y17 9 " "Info: 3: + IC(1.043 ns) + CELL(0.292 ns) = 2.746 ns; Loc. = LAB_X2_Y17; Fanout = 9; COMB Node = 'Equal0~84'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.335 ns" { Equal0~83 Equal0~84 } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(1.225 ns) 4.399 ns \\flag1:Q\[8\] 4 REG LAB_X2_Y17 3 " "Info: 4: + IC(0.428 ns) + CELL(1.225 ns) = 4.399 ns; Loc. = LAB_X2_Y17; Fanout = 3; REG Node = '\\flag1:Q\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.653 ns" { Equal0~84 \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.631 ns ( 37.08 % ) " "Info: Total cell delay = 1.631 ns ( 37.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.768 ns ( 62.92 % ) " "Info: Total interconnect delay = 2.768 ns ( 62.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.399 ns" { \flag1:Q[7] Equal0~83 Equal0~84 \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y11 X11_Y21 " "Info: The peak interconnect region extends from location X0_Y11 to location X11_Y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/EDA/frequency/frequency.fit.smsg " "Info: Generated suppressed messages file F:/EDA/frequency/frequency.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "180 " "Info: Allocated 180 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 14 20:46:58 2009 " "Info: Processing ended: Thu May 14 20:46:58 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 14 20:46:59 2009 " "Info: Processing started: Thu May 14 20:46:59 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off frequency -c frequency " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off frequency -c frequency" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}