{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "f " "Info: Detected ripple clock \"f\" as buffer" {  } { { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 13 -1 0 } } { "d:/eda/quartus_ii_7.1/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/eda/quartus_ii_7.1/quartus/bin/Assignment Editor.qase" 1 { { 0 "f" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register \\flag1:Q\[7\] register \\flag1:Q\[8\] 195.73 MHz 5.109 ns Internal " "Info: Clock \"clk\" has Internal fmax of 195.73 MHz between source register \"\\flag1:Q\[7\]\" and destination register \"\\flag1:Q\[8\]\" (period= 5.109 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.848 ns + Longest register register " "Info: + Longest register to register delay is 4.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\flag1:Q\[7\] 1 REG LC_X2_Y17_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = '\\flag1:Q\[7\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { \flag1:Q[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.590 ns) 1.844 ns Equal0~83 2 COMB LC_X2_Y18_N2 2 " "Info: 2: + IC(1.254 ns) + CELL(0.590 ns) = 1.844 ns; Loc. = LC_X2_Y18_N2; Fanout = 2; COMB Node = 'Equal0~83'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.844 ns" { \flag1:Q[7] Equal0~83 } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.198 ns) + CELL(0.114 ns) 3.156 ns Equal0~84 3 COMB LC_X2_Y17_N9 9 " "Info: 3: + IC(1.198 ns) + CELL(0.114 ns) = 3.156 ns; Loc. = LC_X2_Y17_N9; Fanout = 9; COMB Node = 'Equal0~84'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.312 ns" { Equal0~83 Equal0~84 } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/eda/quartus_ii_7.1/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.467 ns) + CELL(1.225 ns) 4.848 ns \\flag1:Q\[8\] 4 REG LC_X2_Y17_N8 3 " "Info: 4: + IC(0.467 ns) + CELL(1.225 ns) = 4.848 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\\flag1:Q\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { Equal0~84 \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 39.79 % ) " "Info: Total cell delay = 1.929 ns ( 39.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.919 ns ( 60.21 % ) " "Info: Total interconnect delay = 2.919 ns ( 60.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { \flag1:Q[7] Equal0~83 Equal0~84 \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { \flag1:Q[7] Equal0~83 Equal0~84 \flag1:Q[8] } { 0.000ns 1.254ns 1.198ns 0.467ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns \\flag1:Q\[8\] 2 REG LC_X2_Y17_N8 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\\flag1:Q\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns \\flag1:Q\[7\] 2 REG LC_X2_Y17_N7 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = '\\flag1:Q\[7\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk \flag1:Q[7] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[7] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[7] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.848 ns" { \flag1:Q[7] Equal0~83 Equal0~84 \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "4.848 ns" { \flag1:Q[7] Equal0~83 Equal0~84 \flag1:Q[8] } { 0.000ns 1.254ns 1.198ns 0.467ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[7] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[7] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "\\flag1:Q\[8\] ain\[8\] clk 4.782 ns register " "Info: tsu for register \"\\flag1:Q\[8\]\" (data pin = \"ain\[8\]\", clock pin = \"clk\") is 4.782 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.699 ns + Longest pin register " "Info: + Longest pin to register delay is 7.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ain\[8\] 1 PIN PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 1; PIN Node = 'ain\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ain[8] } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.115 ns) + CELL(0.115 ns) 7.699 ns \\flag1:Q\[8\] 2 REG LC_X2_Y17_N8 3 " "Info: 2: + IC(6.115 ns) + CELL(0.115 ns) = 7.699 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\\flag1:Q\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.230 ns" { ain[8] \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 20.57 % ) " "Info: Total cell delay = 1.584 ns ( 20.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.115 ns ( 79.43 % ) " "Info: Total interconnect delay = 6.115 ns ( 79.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "7.699 ns" { ain[8] \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "7.699 ns" { ain[8] ain[8]~out0 \flag1:Q[8] } { 0.000ns 0.000ns 6.115ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns \\flag1:Q\[8\] 2 REG LC_X2_Y17_N8 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\\flag1:Q\[8\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk \flag1:Q[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "7.699 ns" { ain[8] \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "7.699 ns" { ain[8] ain[8]~out0 \flag1:Q[8] } { 0.000ns 0.000ns 6.115ns } { 0.000ns 1.469ns 0.115ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[8] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q \\flag2:t 8.601 ns register " "Info: tco from clock \"clk\" to destination pin \"q\" through register \"\\flag2:t\" is 8.601 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.664 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns f 2 REG LC_X2_Y17_N9 1 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X2_Y17_N9; Fanout = 1; REG Node = 'f'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk f } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.711 ns) 4.664 ns \\flag2:t 3 REG LC_X1_Y17_N2 2 " "Info: 3: + IC(0.775 ns) + CELL(0.711 ns) = 4.664 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = '\\flag2:t'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { f \flag2:t } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 66.79 % ) " "Info: Total cell delay = 3.115 ns ( 66.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 33.21 % ) " "Info: Total interconnect delay = 1.549 ns ( 33.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.664 ns" { clk f \flag2:t } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "4.664 ns" { clk clk~out0 f \flag2:t } { 0.000ns 0.000ns 0.774ns 0.775ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.713 ns + Longest register pin " "Info: + Longest register to pin delay is 3.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\flag2:t 1 REG LC_X1_Y17_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = '\\flag2:t'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { \flag2:t } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.589 ns) + CELL(2.124 ns) 3.713 ns q 2 PIN PIN_8 0 " "Info: 2: + IC(1.589 ns) + CELL(2.124 ns) = 3.713 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { \flag2:t q } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.20 % ) " "Info: Total cell delay = 2.124 ns ( 57.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.589 ns ( 42.80 % ) " "Info: Total interconnect delay = 1.589 ns ( 42.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { \flag2:t q } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { \flag2:t q } { 0.000ns 1.589ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.664 ns" { clk f \flag2:t } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "4.664 ns" { clk clk~out0 f \flag2:t } { 0.000ns 0.000ns 0.774ns 0.775ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.713 ns" { \flag2:t q } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "3.713 ns" { \flag2:t q } { 0.000ns 1.589ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}