{ "Info" "ITDB_TH_RESULT" "\\flag1:Q\[6\] ain\[6\] clk -3.597 ns register " "Info: th for register \"\\flag1:Q\[6\]\" (data pin = \"ain\[6\]\", clock pin = \"clk\") is -3.597 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns \\flag1:Q\[6\] 2 REG LC_X2_Y17_N6 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N6; Fanout = 4; REG Node = '\\flag1:Q\[6\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk \flag1:Q[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[6] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.566 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ain\[6\] 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'ain\[6\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ain[6] } "NODE_NAME" } } { "frequency.vhd" "" { Text "F:/EDA/frequency/frequency.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.982 ns) + CELL(0.115 ns) 6.566 ns \\flag1:Q\[6\] 2 REG LC_X2_Y17_N6 4 " "Info: 2: + IC(4.982 ns) + CELL(0.115 ns) = 6.566 ns; Loc. = LC_X2_Y17_N6; Fanout = 4; REG Node = '\\flag1:Q\[6\]'" {  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.097 ns" { ain[6] \flag1:Q[6] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 24.12 % ) " "Info: Total cell delay = 1.584 ns ( 24.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.982 ns ( 75.88 % ) " "Info: Total interconnect delay = 4.982 ns ( 75.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.566 ns" { ain[6] \flag1:Q[6] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "6.566 ns" { ain[6] ain[6]~out0 \flag1:Q[6] } { 0.000ns 0.000ns 4.982ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk \flag1:Q[6] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 \flag1:Q[6] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda/quartus_ii_7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.566 ns" { ain[6] \flag1:Q[6] } "NODE_NAME" } } { "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda/quartus_ii_7.1/quartus/bin/Technology_Viewer.qrui" "6.566 ns" { ain[6] ain[6]~out0 \flag1:Q[6] } { 0.000ns 0.000ns 4.982ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 14 20:50:03 2009 " "Info: Processing ended: Thu May 14 20:50:03 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}