# Synplicity, Inc. constraint file
# C:\1553\syn\encoder_1553.sdc
# Written on Thu Dec 18 10:50:20 2003
# by Synplify Pro, 7.3.3      Scope Editor

#
# Clocks
#
define_clock            -name {enc_clk}  -freq 2.000 -clockgroup default_clkgroup

#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_input_delay               -default  50.00 -improve 0.00 -route 0.00 -ref {enc_clk:r}
define_output_delay              -default  50.00 -improve 0.00 -route 0.00 -ref {enc_clk:r}
define_input_delay -disable      {rst_n} -improve 0.00 -route 0.00
define_output_delay -disable     {tx_busy} -improve 0.00 -route 0.00
define_input_delay -disable      {tx_csw} -improve 0.00 -route 0.00
define_output_delay -disable     {tx_data} -improve 0.00 -route 0.00
define_output_delay -disable     {tx_dval} -improve 0.00 -route 0.00
define_input_delay -disable      {tx_dw} -improve 0.00 -route 0.00
define_input_delay -disable      {tx_dword[0:15]} -improve 0.00 -route 0.00

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#
define_false_path           -from {p:rst_n} 

#
# Delay Path
#

#
# Attributes
#

#
# Other Constraints
#