; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; PWM.vhd                          ; yes             ; User VHDL File  ; D:/程序/PWM/PWM.vhd          ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 73    ;
;                                             ;       ;
; Total combinational functions               ; 73    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 29    ;
;     -- 3 input functions                    ; 21    ;
;     -- <=2 input functions                  ; 23    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 47    ;
;     -- arithmetic mode                      ; 26    ;
;                                             ;       ;
; Total registers                             ; 31    ;
;     -- Dedicated logic registers            ; 31    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 6     ;
; Maximum fan-out node                        ; reset ;
; Maximum fan-out                             ; 31    ;
; Total fan-out                               ; 322   ;
; Average fan-out                             ; 2.93  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |PWM                       ; 73 (73)           ; 31 (31)      ; 0           ; 0            ; 0       ; 0         ; 6    ; 0            ; |PWM                ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-------------------------------+
; State Machine - |PWM|s        ;
+-------+-------+-------+-------+
; Name  ; s.st2 ; s.st1 ; s.st0 ;
+-------+-------+-------+-------+
; s.st0 ; 0     ; 0     ; 0     ;
; s.st1 ; 0     ; 1     ; 1     ;
; s.st2 ; 1     ; 0     ; 1     ;
+-------+-------+-------+-------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; count1[8]                             ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 31    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 30    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; H[5]                                   ; 2       ;
; H[4]                                   ; 2       ;
; H[1]                                   ; 2       ;
; clkout                                 ; 9       ;
; ss[0]                                  ; 6       ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 4 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |PWM|H[6]                  ;
; 6:1                ; 3 bits    ; 12 LEs        ; 3 LEs                ; 9 LEs                  ; Yes        ; |PWM|ss[3]                 ;
; 6:1                ; 3 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |PWM|H[5]                  ;
; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |PWM|Selector0             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Mon May 25 13:04:51 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PWM -c PWM
Info: Found 2 design units, including 1 entities, in source file PWM.vhd
    Info: Found design unit 1: PWM-Behavioral
    Info: Found entity 1: PWM
Info: Elaborating entity "PWM" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at PWM.vhd(56): object "bclk0" assigned a value but never read
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Critical Warning: Ignored Power-Up Level option on the following registers
    Critical Warning: Register H[5] will power up to High
    Critical Warning: Register H[4] will power up to High
    Critical Warning: Register H[1] will power up to High
    Critical Warning: Register ss[0] will power up to High
Info: Implemented 82 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 1 output pins
    Info: Implemented 76 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 187 megabytes
    Info: Processing ended: Mon May 25 13:04:53 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02