XAPP610  Zip file contains 

The word document for DCT

Verilog files (*.v)
    dct.v
    test_dct.v

Vhdl file (*.vhd)
   dct.vhd

The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i. 
The multiplier instantiation in the verilog files are used when targeting Virtex 2. For all other devices, 
the instantiations are commented out and the behavioral multiplier code is used. Test_dct contains the 
test bench which uses the input values as given in the reference "Image and Video Compression Standards" 
by V. Bhaskaran and K. Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v 
and idct.v files.  The lower level vhdl files are dct.vhd and idct.vhd