//Maxwell GPU!!
//run at 6.25MHz
`define delay 8
module QJSTDOUT2 (nreset,vclk,data_validin,nblank,nsync,hblank,hsync,cblank,csync,
						int,rst,fen,gy,mc,len,tempint,ciflv,ciffv);
input nreset,vclk;
input data_validin;

output nblank,nsync;
output hblank,hsync;
output cblank,csync,ciflv,ciffv;

output int,rst,fen;
output mc,len;
output tempint;
output [9:0] gy;

reg [9:0]	gy;
reg csync,hsync,ciffv,ciflv;
reg cblank;
reg fen,rst,int;
//reg len;
//=======================================================

reg [8:0] lclknum;
reg [8:0] delay;
reg [17:0] lclknum_wei;
//reg temprst;
reg [10:0] hlnum;
reg hblank;
reg tempint;
reg tempfen;
reg junheng,junheng_en;
wire cc;
reg len,len1,len2,len3;
//=======================================================
assign mc=vclk;
//assign len=data_validin;
//assign len=~hblank;
always @(posedge vclk) len3<=data_validin;
always @(posedge vclk) len2<=len3;
always @(posedge vclk) len1<=len2;
always @(posedge vclk) len<=len1;
//always @(posedge vclk) if(lclknum<320) len<=1; else len<=0;
always @(posedge vclk) 
      if(lclknum_wei>=delay)
        if(lclknum==399)lclknum<=0; 
        else lclknum<=lclknum+1;
always @(negedge vclk) if(lclknum==399)ciflv<=1; else ciflv<=0;

always @ (posedge vclk) if(lclknum<320) hblank<=0; else hblank<=1;
//assign hblank=~data_validin;
always @ (posedge vclk) if(lclknum>334 && lclknum<364) hsync<=1;else hsync<=0;
//===============int============================
//always @(posedge vclk) if(lclknum>65 && lclknum<383) tempint<=1;
//					else tempint<=0;

always @(posedge vclk) if(lclknum==66)tempint<=1;
						else if(lclknum==382) tempint<=0;
						
always @ (posedge vclk) if((hlnum>33 && hlnum<562 ) 
						||(hlnum>659 && hlnum<1186 ) ) int<=tempint;
						else int<=0;
always @ (negedge vclk) if(lclknum==399) 
                          if(hlnum==51||hlnum==675)ciffv<=1;
                          else ciffv<=0;
                        else ciffv<=0;   

always @(posedge vclk) if(lclknum==199 || lclknum==399) 
							if(hlnum==1249)hlnum<=0;
							else hlnum<=hlnum+1;

//always wait(nreset==1) lclknum_wei<=0;
//       wait(nreset==0) lclknum_wei<=lclknum_wei+1;	
always @(posedge vclk) if(nreset==1) lclknum_wei<=0;
                       else	lclknum_wei<=lclknum_wei+1;					
always @(posedge vclk) if(hlnum==40 || hlnum == 664) rst<=1'b1; else rst<=1'b0;

always @(posedge vclk)
	if(lclknum==388)
	begin
		 if(hlnum==41 || hlnum==665)  fen<=1'b1;
		else if( hlnum== 521 || hlnum==1145) fen<=1'b0;
	end		
	
//always @(negedge hblank )cblank<=(~fen);
//assign cblank=~fen;

always @(posedge vclk)
	if(lclknum==399)
	begin
		 if(hlnum==51 || hlnum==675)  cblank<=1'b0;
		else if( hlnum== 531 || hlnum==1155) cblank<=1'b1;
	end	
/*	
always @(posedge vclk) if((hlnum>51 && hlnum<532)||( hlnum>679 && hlnum<1160))cblank<=1'b0;
					else cblank<=1'b1;
*/
always @(posedge vclk) if((hlnum>=580 && hlnum<=585) ||
						( hlnum>=1205 && hlnum<=1210)) csync<=1'b1; 
					else csync<=1'b0;

/*always @(posedge vclk) if(hlnum==580 || hlnum==1205) csync<=1'b1; 
					else if( hlnum== 583 || hlnum==1208) csync<=1'b0;
*/
assign nblank=~((hblank|cblank));
assign nsync= ~((csync^hsync^cc));

always @(posedge vclk)
begin
	gy[9:1]<=lclknum[8:0];
end

always @(posedge vclk) if(lclknum==149 || lclknum==349) junheng<=1'b1; 
					else if( lclknum== 164 || lclknum==364) junheng<=1'b0;

always @(posedge vclk) if(hlnum==575 || hlnum==586|| hlnum==1200|| hlnum==1211) junheng_en<=1'b1; 
					else if( hlnum== 579 || hlnum==590 || hlnum==1204 || hlnum==1215) junheng_en<=1'b0;
assign cc=junheng & junheng_en;

endmodule