?? syn_gen.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity syn_gen is
port(clk,syn_in:in std_logic;
syn_out:out std_logic
);
end syn_gen;
architecture rtl of syn_gen is
signal syn_flag:std_logic;
signal syn_count:std_logic_vector(14 downto 0);
begin
process(syn_in)
begin
if(syn_count=25000) then
syn_flag<='0';
elsif(syn_in'event and syn_in='0') then
syn_flag<='1';
end if;
end process;
syn_out<=syn_flag;
process(clk)
begin
if(clk'event and clk='1') then
if(syn_flag='1') then
syn_count<=syn_count+'1';
else
syn_count<=(others=>'0');
end if;
end if;
end process;
end rtl;
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