library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity crc is
   port (
   clk: in std_logic;
   reset_n:in std_logic;
   din: in std_logic;
   dout: out std_logic_vector(3 downto 0)
   );
end crc;

architecture crc_arch of crc is
signal d1,d2:std_logic;
signal d:std_logic_vector(3 downto 0):=(others =>'0');


begin
    d1 <= d(0) xor din;
    d2 <= d(3) xor '1';    
process(clk ,reset_n)
begin
    
    if (clk'event and clk ='1') then
      if (reset_n ='0') then -- 同步復位
         d <= (others => '0');-- CRC 碼置零
      else
         if (d1 = '1') then
              d <= d1&d2&d(2 downto 1);
          elsif (d1 = '0') then
              d <= d1&d(3 downto 1);
          end if ;
      end if ;
      dout <=d;
 end if ;
end process ;
end crc_arch;